100 lines
3.6 KiB
Markdown
100 lines
3.6 KiB
Markdown
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# Intel DG43GT
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This page describes how to run coreboot on the [Intel DG43GT] desktop.
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## Flashing coreboot
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```eval_rst
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+---------------------+------------+
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| Type | Value |
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+=====================+============+
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| Socketed flash | no |
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+---------------------+------------+
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| Model | W25X32 |
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+---------------------+------------+
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| Size | 4 MiB |
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+---------------------+------------+
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| In circuit flashing | NO! |
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+---------------------+------------+
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| Package | SOIC-8 |
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+---------------------+------------+
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| Write protection | No |
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+---------------------+------------+
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| Dual BIOS feature | No |
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+---------------------+------------+
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| Internal flashing | yes |
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+---------------------+------------+
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```
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### Internal programming
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The SPI flash can be accessed internally using [flashrom].
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Only the BIOS region can and needs to be written to.
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```bash
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$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
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```
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### External programming
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ISP (in circuit programming) seems to be impossible on this board, which
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is a property it shares with many boards featuring the ICH10 southbridge.
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**Recovering from a bad flash will require desoldering the flash!**
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Desoldering the SPI flash can easily be done with a hot air station.
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Apply some flux around the SPI flash, set the hot air station to 350-400°C
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and after heating the chip up for a minute it should be possible to remove it.
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Having removed the flash chip, you can reprogram it externally then resolder
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it using a soldering iron.
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Another option would be to hook up a SPI flash (socket) to the SPI header,
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for easier flash removing in the future (if you expect to be hacking on this
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board). To do this you first need to solder the SPI header to the board.
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**NOTE: This header cannot be used for ISP either.**
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**NOTE2: Don't forget to connect the WP# and HOLD# pin on the SPI flash to 3.3V.**
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The layout of the header is:
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```
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+---+---+
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GND <- | x | x | -> SPI_CLK
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+---+---+
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3VSB <- | x | x | -> SPI_MISO
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+---+---+
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| | x | -> SPI_MOSI
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+---+---+
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SPI_CS# <-| x | x | -> SPI_CS# (again)
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+---+---+
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```
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**Picture of the board with the flash hooked on externally**
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![][dg43gt_full]
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**Close up picture of the SPI flash pads and recovery header**
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![][dg43gt_closeup]
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[dg43gt_full]: dg43gt_full.jpg
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[dg43gt_closeup]: dg43gt_closeup.jpg
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## Technology
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```eval_rst
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+------------------+---------------------------------------------------+
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| Northbridge | Intel G43 (called x4x in coreboot code) |
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+------------------+---------------------------------------------------+
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| Southbridge | Intel ICH10 (called i82801jx in coreboot code) |
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+------------------+---------------------------------------------------+
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| CPU (LGA775) | model f4x, f6x, 6fx, 1067x (pentium 4, d, core 2) |
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+------------------+---------------------------------------------------+
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| SuperIO | Winbond W83627DHG |
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+------------------+---------------------------------------------------+
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| Coprocessor | Intel ME (optionally enabled) |
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+------------------+---------------------------------------------------+
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| Clockgen (CK505) | SLG8XP549T |
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+------------------+---------------------------------------------------+
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```
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[Intel DG43GT]: https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT
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[flashrom]: https://flashrom.org/Flashrom
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