98 lines
3.8 KiB
Markdown
98 lines
3.8 KiB
Markdown
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# PC Engines APU1
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This page describes how to run coreboot on PC Engines APU1 platform.
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## Technology
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```eval_rst
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+------------+--------------------------------------------------------+
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| CPU | AMD G series T40E APU |
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+------------+--------------------------------------------------------+
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| CPU core | 1 GHz dual core (Bobcat core) with 64 bit support |
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| | 32K data + 32K instruction + 512KB L2 cache per core |
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+------------+--------------------------------------------------------+
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| DRAM | 2 or 4 GB DDR3-1066 DRAM |
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+------------+--------------------------------------------------------+
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| Boot | From SD card, USB, mSATA, SATA |
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+------------+--------------------------------------------------------+
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| Power | 6 to 12W of 12V power |
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+------------+--------------------------------------------------------+
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| Firmware | coreboot with support for iPXE and USB boot |
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+------------+--------------------------------------------------------+
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```
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## Flashing coreboot
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```eval_rst
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+---------------------+--------------------------+
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| Type | Value |
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+=====================+==========================+
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| Socketed flash | no |
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+---------------------+--------------------------+
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| Model | MX25L1606E |
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+---------------------+--------------------------+
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| Size | 2 MiB |
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+---------------------+--------------------------+
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| Package | SOP-8 |
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+---------------------+--------------------------+
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| Write protection | jumper on WP# pin |
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+---------------------+--------------------------+
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| Dual BIOS feature | no |
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+---------------------+--------------------------+
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| Internal flashing | yes |
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+---------------------+--------------------------+
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```
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### Internal programming
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The SPI flash can be accessed using [flashrom]. It is important to execute
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command with a `-c <chipname>` argument:
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flashrom -p internal -c "MX25L1606E" -w coreboot.rom
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### External programming
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**IMPORTANT**: When programming SPI flash, first you need to enter apu1 in S5
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(Soft-off) power state. S5 state can be forced by shorting power button pin on
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J2 header.
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The external access to flash chip is available through standard SOP-8 clip or
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SOP-8 header next to the flash chip on the board. Notice that not all boards
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have a header soldered down originally. Hence, there could be an empty slot with
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8 eyelets, so you can solder down a header on your own. The SPI flash chip and
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SPI header are marked in the picture below. Also there is SPI header pin layout
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included. Notice, that signatures at the schematic can be ambiguous:
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- J12 SPIDI = U35 SO = MISO
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- J12 SPIDO = U35 SI = MOSI
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There is no restrictions as to the programmer device. It is only recommended to
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flash firmware without supplying power. External programming can be performed,
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for example using OrangePi and Armbian. You can exploit linux_spi driver which
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provide communication with SPI devices. Example command to program SPI flash
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with OrangePi using linux_spi:
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flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c
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"MX25L1606E"
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**apu1 platform with marked in SPI header and SPI flash chip**
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![][apu1c1_flash]
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**SPI header pin layout**
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![][spi_header]
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### Schematics
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PC Engines APU platform schematics are available for free on PC Engines official
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site. Depending on the configuration:
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[apu1c](https://www.pcengines.ch/schema/apu1c.pdf) and
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[apu1d](https://www.pcengines.ch/schema/apu1d.pdf).
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[apu1c1_flash]: apu1c1.jpg
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[spi_header]: apu1_spi.jpg
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[flashrom]: https://flashrom.org/Flashrom
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