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AUTHORS, util/: Drop individual copyright notices We have the git history which is a more reliable librarian. Change-Id: Idbcc5ceeb33804204e56d62491cb58146f7c9f37 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-05-08 19:28:13 +02:00
/* This file is part of the superiotool project */
util/: Replace GPLv2 boiler plate with SPDX header Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|This[\s*]*program[\s*]*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.*[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*This[\s*#]*program[\s*#]*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.*[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: I1008a63b804f355a916221ac994701d7584f60ff Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08 20:48:04 +02:00
/* SPDX-License-Identifier: GPL-2.0-or-later */
Add missing files from the last commit (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 02:47:58 +01:00
#include "superiotool.h"
#define DEVICE_ID_VT82C686_REG 0xe0
#define DEVICE_REV_VT82C686_REG 0xe1
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
#define DEVICE_ID_VT1211_REG 0x20
#define DEVICE_REV_VT1211_REG 0x21
Add missing files from the last commit (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 02:47:58 +01:00
static const struct superio_registers reg_table[] = {
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
{0x3c00, "VT82C686A/VT82C686B", {
{EOT}}},
{0x3c01, "VT1211", {
util/superiotool: dump VT1211 registers Change-Id: Id01b72a2194ebf3359a11c3ff382efaedf28f9e1 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:23 +01:00
{NOLDN, NULL,
{0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,
0x2e,0x2f,EOT},
{0x3c,0x01,0x00,0x11,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,EOT}},
{0x0, "Floppy Disk Controller (FDC)",
{0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT},
{0x00,0x03,0xf0,0x06,0x01,0x00,0x00,EOT}},
{0x1, "Parallel Port (PP)",
{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
{0x03,0x03,0x78,0x05,0x00,0x00,EOT}},
{0x2, "Serial Port 1 (UART1)",
{0x30,0x60,0x61,0x70,0xf0,EOT},
{0x00,0x03,0xf8,0x04,0x00,EOT}},
{0x3, "Serial Port 2 (UART2)",
{0x30,0x60,0x61,0x70,0xf0,EOT},
{0x00,0x02,0xf8,0x03,0x00,EOT}},
{0x6, "MIDI",
{0x30,0x60,0x61,0x70,EOT},
{0x00,0x03,0x30,0x00,EOT}},
{0x7, "Game Port (GMP)",
{0x30,0x60,0x61,EOT},
{0x00,0x02,0x00,EOT}},
{0x8, "GPIO",
{0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT},
{0x00,0xe9,0x00,0x00,0x00,0x00,0x00,EOT}},
{0x9, "Watch Dog (WDG)",
{0x30,0x60,0x61,0x70,0xf0,EOT},
{0x00,0xea,0x00,0x00,0x00,EOT}},
{0xa, "Wake-up Control (WUC)",
{0x30,0x60,0x61,0x70,EOT},
{0x00,0xeb,0x00,0x00,EOT}},
{0xb, "Hardware Monitor (HM)",
{0x30,0x60,0x61,0x70,EOT},
{0x00,0xec,0x00,0x00,EOT}},
{0xc, "Very Fast IR (VFIR)",
{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
{0x00,0xe8,0x00,0x00,0x06,0x00,EOT}},
{0xd, "Flash ROM (ROM)",
{0x30,0xf0,EOT},
{0x01,0x00,EOT}},
Add missing files from the last commit (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 02:47:58 +01:00
{EOT}}},
{EOT}
};
static uint8_t vt82c686_conf = 0;
static int enter_conf_mode_via_vt82c686(void)
{
struct pci_dev *dev;
dev = pci_dev_find(0x1106, 0x0686);
if (!dev) {
if (verbose)
printf(" PCI device 1106:0686 not found.\n");
return 1;
}
vt82c686_conf = pci_read_byte(dev, 0x85);
if (verbose)
printf(" Super I/O %sabled, Super I/O configuration %sabled\n",
(vt82c686_conf & (1 << 0)) ? "en" : "dis",
(vt82c686_conf & (1 << 1)) ? "en" : "dis");
/* If the Super I/O is not enabled, skip it. */
if (!(vt82c686_conf & (1 << 0)))
return 1;
/* Enable Super I/O configuration mode. */
pci_write_byte(dev, 0x85, vt82c686_conf | (1 << 1));
return 0;
}
static void exit_conf_mode_via_vt82c686(void)
{
struct pci_dev *dev;
dev = pci_dev_find(0x1106, 0x0686);
if (!dev) {
printf("Bug: PCI device 1106:0686 not found during shutdown.\n"
"Please report to coreboot@coreboot.org.\n");
return;
}
/* Restore (disable?) Super I/O configuration mode setting. */
pci_write_byte(dev, 0x85, vt82c686_conf);
}
void probe_idregs_via(uint16_t port)
{
uint16_t id;
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
uint8_t devid;
Add missing files from the last commit (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 02:47:58 +01:00
uint8_t rev;
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
if (port == 0x3f0) {
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
probing_for("VIA", "(init=vt82c686) ", port);
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
if (enter_conf_mode_via_vt82c686())
return;
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
devid = regval(port, DEVICE_ID_VT82C686_REG);
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
rev = regval(port, DEVICE_REV_VT82C686_REG);
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
id = devid << 8;
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
if (superio_unknown(reg_table, id)) {
if (verbose)
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
printf(NOTFOUND "id=0x%02x, rev=0x%02x\n", devid, rev);
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
} else {
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
printf("Found VIA %s (id=0x%02x, rev=0x%02x) at 0x%x\n",
get_superio_name(reg_table, id), devid, rev, port);
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
chip_found = 1;
}
Add missing files from the last commit (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 02:47:58 +01:00
exit_conf_mode_via_vt82c686();
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
if (chip_found)
return;
} else {
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
probing_for("VIA", "(init=0x87,0x87) ", port);
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
enter_conf_mode_winbond_fintek_ite_8787(port);
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
devid = regval(port, DEVICE_ID_VT1211_REG);
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
rev = regval(port, DEVICE_REV_VT1211_REG);
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
id = (devid << 8) | 1;
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
if (superio_unknown(reg_table, id)) {
if (verbose)
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
printf(NOTFOUND "id=0x%02x, rev=0x%02x\n", devid, rev);
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
} else {
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
printf("Found VIA %s (id=0x%02x, rev=0x%02x) at 0x%x\n",
get_superio_name(reg_table, id), devid, rev, port);
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
chip_found = 1;
util/superiotool: distinguish between VT82C686 and VT1211 They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:18 +01:00
dump_superio("VIA", reg_table, port, id, LDN_SEL);
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
}
Add missing files from the last commit (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 02:47:58 +01:00
}
util/superiotool: recognize a VT1211 LPC superio Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-31 09:25:05 +01:00
exit_conf_mode_winbond_fintek_ite_8787(port);
Add missing files from the last commit (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 02:47:58 +01:00
}
void print_via_chips(void)
{
print_vendor_chips("VIA", reg_table);
}