84 lines
2.9 KiB
C
84 lines
2.9 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <reg_script.h>
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#include <baytrail/iosf.h>
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#include <baytrail/ramstage.h>
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static const struct reg_script scc_start_dll[] = {
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/* Configure master DLL. */
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REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000),
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/* Configure Swing,FSM for Master DLL */
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REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133),
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/* Run+Local Reset on Master DLL */
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REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933),
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REG_SCRIPT_END,
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};
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static const struct reg_script scc_after_dll[] = {
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/* Configure Write Path */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad),
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/* Configure Read Path */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad),
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/* eMMC 4.5 TX and RX DLL */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0),
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/* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0),
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/*
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* iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01
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* iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01
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*/
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REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5),
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/* Enable IOSF Snoop */
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REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)),
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/* SDIO 3V Support. */
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REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30),
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REG_SCRIPT_END,
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};
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void baytrail_init_scc(void)
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{
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uint32_t dll_values;
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printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n");
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/* Common Sideband Initialization for SCC */
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reg_script_run(scc_start_dll);
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/* Override Slave Path - populate DLL settings. */
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dll_values = iosf_score_read(0x496c) & 0x7ffff;
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dll_values |= iosf_score_read(0x4950) & ~0xfffff;
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iosf_score_write(0x4950, dll_values | (1 << 19));
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reg_script_run(scc_after_dll);
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}
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