109 lines
2.6 KiB
C
109 lines
2.6 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef INTEL_LYNXPOINT_LP_GPIO_H
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#define INTEL_LYNXPOINT_LP_GPIO_H
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/* LynxPoint LP GPIOBASE Registers */
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#define GPIO_OWNER(set) (0x00 + ((set) * 4))
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#define GPIO_PIRQ_APIC_EN 0x10
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#define GPIO_BLINK 0x18
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#define GPIO_SER_BLINK 0x1c
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#define GPIO_SER_BLINK_CS 0x20
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#define GPIO_SER_BLINK_DATA 0x24
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#define GPIO_ROUTE(set) (0x30 + ((set) * 4))
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#define GPIO_RESET(set) (0x60 + ((set) * 4))
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#define GPIO_GLOBAL_CONFIG 0x7c
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#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4))
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#define GPIO_IRQ_IE(set) (0x90 + ((set) * 4))
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#define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8))
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#define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8))
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#define MAX_GPIO_NUMBER 94 /* zero based */
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#define GPIO_LIST_END 0xff
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/* conf0 */
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#define GPIO_MODE_NATIVE (0 << 0)
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#define GPIO_MODE_GPIO (1 << 0)
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#define GPIO_DIR_OUTPUT (0 << 2)
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#define GPIO_DIR_INPUT (1 << 2)
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#define GPIO_NO_INVERT (0 << 3)
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#define GPIO_INVERT (1 << 3)
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#define GPIO_IRQ_EDGE (0 << 4)
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#define GPIO_IRQ_LEVEL (1 << 4)
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#define GPI_LEVEL (1 << 30)
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#define GPO_LEVEL_LOW (0 << 31)
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#define GPO_LEVEL_HIGH (1 << 31)
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/* conf1 */
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#define GPIO_PULL_NONE (0 << 0)
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#define GPIO_PULL_DOWN (1 << 0)
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#define GPIO_PULL_UP (2 << 0)
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#define GPIO_SENSE_ENABLE (0 << 2)
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#define GPIO_SENSE_DISABLE (1 << 2)
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/* owner */
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#define GPIO_OWNER_ACPI 0
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#define GPIO_OWNER_GPIO 1
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/* route */
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#define GPIO_ROUTE_SCI 0
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#define GPIO_ROUTE_SMI 1
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/* irqen */
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#define GPIO_IRQ_DISABLE 0
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#define GPIO_IRQ_ENABLE 1
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/* blink */
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#define GPO_NO_BLINK 0
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#define GPO_BLINK 1
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/* reset */
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#define GPIO_RESET_PWROK 0
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#define GPIO_RESET_RSMRST 1
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struct pch_lp_gpio_map {
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u8 gpio;
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u32 conf0;
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u32 conf1;
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u8 owner;
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u8 route;
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u8 irqen;
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u8 reset;
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u8 blink;
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} __attribute__ ((packed));
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/* Configure GPIOs with mainboard provided settings */
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void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
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#endif
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