2010-05-05 13:19:50 +02:00
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/*
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* sconfig, coreboot device tree compiler
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*
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* Copyright (C) 2010 coresystems GmbH
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2016-05-07 10:11:14 +02:00
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* written by Patrick Georgi <patrick@georgi-clan.de>
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2010-05-05 13:19:50 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include <errno.h>
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struct resource;
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struct resource {
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int type;
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int index;
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int base;
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struct resource *next;
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};
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struct reg;
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struct reg {
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char *key;
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char *value;
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struct reg *next;
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};
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2012-06-21 22:19:48 +02:00
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struct pci_irq_info {
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int ioapic_irq_pin;
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int ioapic_dst_id;
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};
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2018-05-31 00:09:09 +02:00
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2018-05-31 19:33:16 +02:00
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struct chip;
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struct chip_instance {
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2018-05-31 00:09:09 +02:00
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/*
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* Monotonically increasing ID for each newly allocated
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* node(chip/device).
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*/
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int id;
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2018-05-31 19:33:16 +02:00
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/* Pointer to registers for this chip. */
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struct reg *reg;
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/* Pointer to chip of which this is instance. */
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struct chip *chip;
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/* Pointer to next instance of the same chip. */
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struct chip_instance *next;
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2018-06-22 18:19:15 +02:00
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/*
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* Reference count - Indicates how many devices hold pointer to this
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* chip instance.
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*/
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int ref_count;
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2018-05-31 19:33:16 +02:00
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};
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struct chip {
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2018-05-31 00:09:09 +02:00
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/* Indicates if chip header exists for this chip. */
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int chiph_exists;
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/* Name of current chip. */
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char *name;
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/* Name of current chip normalized to _. */
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char *name_underscore;
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2018-05-31 19:33:16 +02:00
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/* Pointer to first instance of this chip. */
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struct chip_instance *instance;
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2018-05-31 00:09:09 +02:00
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/* Pointer to next chip. */
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struct chip *next;
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};
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2010-05-05 13:19:50 +02:00
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struct device;
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2018-06-03 13:22:17 +02:00
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struct bus {
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/* Instance/ID of the bus under the device. */
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int id;
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/* Pointer to device to which this bus belongs. */
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struct device *dev;
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/* Pointer to list of children. */
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struct device *children;
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/* Pointer to next bus for the device. */
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struct bus *next_bus;
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};
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2010-05-05 13:19:50 +02:00
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struct device {
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2018-06-03 13:22:17 +02:00
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/* Monotonically increasing ID for the device. */
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2010-05-05 13:19:50 +02:00
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int id;
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2018-06-03 13:22:17 +02:00
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2018-09-10 04:51:26 +02:00
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/* Indicates device status (enabled / hidden or not). */
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2010-05-05 13:19:50 +02:00
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int enabled;
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2018-09-10 04:51:26 +02:00
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int hidden;
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Add configurable ramstage support for minimal PCI scanning
This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.
To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.
Some devices must be scanned in all cases, such as 0:0.0.
To indicate which devices we must scan, we add a new mandatory
keyword to sconfig
It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.
We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.
Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.
TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch
Before CL:
Total Boot time: ~685ms
After CL:
Total Boot time: ~615ms
Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2019-10-22 04:02:24 +02:00
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/* non-zero if the device should be included in all cases */
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int mandatory;
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2018-06-03 13:22:17 +02:00
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/* Subsystem IDs for the device. */
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2011-03-01 20:58:15 +01:00
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int subsystem_vendor;
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int subsystem_device;
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int inherit_subsystem;
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2018-06-03 13:22:17 +02:00
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/* Name of this device. */
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2010-05-05 13:19:50 +02:00
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char *name;
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2018-06-03 13:22:17 +02:00
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/* Path of this device. */
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2010-05-05 13:19:50 +02:00
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char *path;
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int path_a;
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int path_b;
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2018-06-03 13:22:17 +02:00
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/* Type of bus that exists under this device. */
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2010-05-05 13:19:50 +02:00
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int bustype;
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2018-06-03 13:22:17 +02:00
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/* PCI IRQ info. */
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2012-06-21 22:19:48 +02:00
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struct pci_irq_info pci_irq_info[4];
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2018-05-31 00:09:09 +02:00
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2018-06-03 13:22:17 +02:00
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/* Pointer to bus of parent on which this device resides. */
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struct bus *parent;
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/* Pointer to next child under the same parent. */
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2010-05-05 13:19:50 +02:00
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struct device *sibling;
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2018-06-03 13:22:17 +02:00
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/* Pointer to resources for this device. */
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2010-05-05 13:19:50 +02:00
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struct resource *res;
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2018-05-31 00:09:09 +02:00
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2018-06-03 13:22:17 +02:00
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/* Pointer to chip instance for this device. */
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2018-05-31 19:33:16 +02:00
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struct chip_instance *chip_instance;
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2010-05-05 13:19:50 +02:00
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2018-06-03 13:22:17 +02:00
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/* Pointer to list of buses under this device. */
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struct bus *bus;
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/* Pointer to last bus under this device. */
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struct bus *last_bus;
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2019-04-12 14:42:17 +02:00
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/* SMBIOS slot type */
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char *smbios_slot_type;
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/* SMBIOS slot data width */
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char *smbios_slot_data_width;
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/* SMBIOS slot description for reference designation */
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char *smbios_slot_designation;
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/* SMBIOS slot length */
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char *smbios_slot_length;
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2018-06-03 13:22:17 +02:00
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};
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2010-05-05 13:19:50 +02:00
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2018-06-03 13:22:17 +02:00
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extern struct bus *root_parent;
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2018-05-31 19:33:16 +02:00
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2018-06-03 13:22:17 +02:00
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struct device *new_device(struct bus *parent,
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2018-05-31 19:33:16 +02:00
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struct chip_instance *chip_instance,
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2018-05-31 16:52:00 +02:00
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const int bustype, const char *devnum,
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2018-09-10 04:51:26 +02:00
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int status);
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2018-06-03 13:22:17 +02:00
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void add_resource(struct bus *bus, int type, int index, int base);
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void add_pci_subsystem_ids(struct bus *bus, int vendor, int device,
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2016-08-06 02:32:18 +02:00
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int inherit);
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2018-06-03 13:22:17 +02:00
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void add_ioapic_info(struct bus *bus, int apicid, const char *_srcpin,
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2016-08-06 02:32:18 +02:00
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int irqpin);
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2016-05-07 10:11:14 +02:00
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2019-04-12 14:42:17 +02:00
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void add_slot_desc(struct bus *bus, char *type, char *length, char *designation,
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char *data_width);
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2016-05-07 10:11:14 +02:00
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void yyrestart(FILE *input_file);
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2018-05-31 00:09:09 +02:00
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/* Add chip data to tail of queue. */
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void chip_enqueue_tail(void *data);
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/* Retrieve chip data from tail of queue. */
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void *chip_dequeue_tail(void);
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2018-05-31 19:33:16 +02:00
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struct chip_instance *new_chip_instance(char *path);
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void add_register(struct chip_instance *chip, char *name, char *val);
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