2013-03-20 21:43:50 +01:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/amd/amdfam15.h>
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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2013-03-29 15:59:13 +01:00
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#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
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2013-03-20 21:43:50 +01:00
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//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
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#define IO_APIC_ID CONFIG_MAX_CPUS
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extern u8 bus_hudson[3];
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extern u32 bus_type[256];
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extern u32 sbdn_hudson;
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extern u32 apicid_hudson;
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u8 picr_data[] = {
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x1F,0x1F,0x1F,0x1F
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};
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u8 intr_data[0x54] = {
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0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x10,0x11,0x12,0x13
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};
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static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
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{
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mc->mpc_length += length;
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mc->mpc_entry_count++;
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}
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static void my_smp_write_bus(struct mp_config_table *mc,
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unsigned char id, const char *bustype)
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{
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struct mpc_config_bus *mpc;
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mpc = smp_next_mpc_entry(mc);
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memset(mpc, '\0', sizeof(*mpc));
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mpc->mpc_type = MP_BUS;
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mpc->mpc_busid = id;
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memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
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smp_add_mpc_entry(mc, sizeof(*mpc));
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}
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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u32 dword;
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u8 byte;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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memcpy(mc->mpc_oem, "AMD ", 8);
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smp_write_processors(mc);
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get_bus_conf();
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//mptable_write_buses(mc, NULL, &bus_isa);
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my_smp_write_bus(mc, 0, "PCI ");
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my_smp_write_bus(mc, 1, "PCI ");
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bus_isa = 0x02;
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my_smp_write_bus(mc, bus_isa, "ISA ");
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/* I/O APICs: APIC ID Version State Address */
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dword = 0;
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dword = pm_ioread(0x34) & 0xF0;
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dword |= (pm_ioread(0x35) & 0xFF) << 8;
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dword |= (pm_ioread(0x36) & 0xFF) << 16;
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dword |= (pm_ioread(0x37) & 0xFF) << 24;
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/* Set IO APIC ID onto IO_APIC_ID */
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write32 (dword, 0x00);
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write32 (dword + 0x10, IO_APIC_ID << 24);
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apicid_hudson = IO_APIC_ID;
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smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
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/* PIC IRQ routine */
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for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
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outb(byte, 0xC00);
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outb(picr_data[byte], 0xC01);
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}
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/* APIC IRQ routine */
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for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
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outb(byte | 0x80, 0xC00);
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outb(intr_data[byte], 0xC01);
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}
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, int_sign, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
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2013-05-27 18:45:32 +02:00
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/* IOMMU */
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PCI_INT(0x0, 0x0, 0x0, 0x10);
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PCI_INT(0x0, 0x0, 0x1, 0x11);
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PCI_INT(0x0, 0x0, 0x2, 0x12);
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PCI_INT(0x0, 0x0, 0x3, 0x13);
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2013-03-20 21:43:50 +01:00
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/* Internal VGA */
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PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
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PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
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/* SMBUS */
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PCI_INT(0x0, 0x14, 0x0, 0x10);
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/* HD Audio */
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PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
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/* USB */
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PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
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PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
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PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
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PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
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PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
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PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
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PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
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/* sata */
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PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
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PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
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/* on board NIC & Slot PCIE. */
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/* PCI slots */
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/* PCI_SLOT 0. */
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PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
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PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
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PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
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PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
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PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
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PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
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PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
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/* PCIe Lan*/
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PCI_INT(0x0, 0x06, 0x0, 0x13);
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/* FCH PCIe PortA */
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PCI_INT(0x0, 0x15, 0x0, 0x10);
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/* FCH PCIe PortB */
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PCI_INT(0x0, 0x15, 0x1, 0x11);
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/* FCH PCIe PortC */
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PCI_INT(0x0, 0x15, 0x2, 0x12);
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/* FCH PCIe PortD */
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PCI_INT(0x0, 0x15, 0x3, 0x13);
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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