2014-02-24 21:56:34 +01:00
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/*
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* This file is part of the coreboot project.
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*
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2015-03-17 17:43:44 +01:00
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* Copyright 2015 Google Inc.
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2015-01-09 14:14:20 +01:00
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* Copyright (C) 2014 Imagination Technologies
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2019-06-14 14:36:37 +02:00
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* Copyright (C) 2018 Eltan B.V.
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2014-02-24 21:56:34 +01:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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2015-03-17 17:43:44 +01:00
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#ifndef PROGRAM_LOADING_H
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#define PROGRAM_LOADING_H
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2014-02-24 21:56:34 +01:00
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2019-01-28 10:22:22 +01:00
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#include <bootmem.h>
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2015-12-08 21:34:35 +01:00
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#include <commonlib/region.h>
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2014-02-24 21:56:34 +01:00
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#include <stdint.h>
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#include <stddef.h>
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2015-03-20 15:42:05 +01:00
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enum {
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/* Last segment of program. Can be used to take different actions for
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* cache maintenance of a program load. */
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SEG_FINAL = 1 << 0,
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};
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2015-12-08 21:34:35 +01:00
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enum prog_type {
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2018-05-21 20:30:17 +02:00
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PROG_UNKNOWN,
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Introduce bootblock self-decompression
Masked ROMs are the silent killers of boot speed on devices without
memory-mapped SPI flash. They often contain awfully slow SPI drivers
(presumably bit-banged) that take hundreds of milliseconds to load our
bootblock, and every extra kilobyte of bootblock size has a hugely
disproportionate impact on boot speed. The coreboot timestamps can never
show that component, but it impacts our users all the same.
This patch tries to alleviate that issue a bit by allowing us to
compress the bootblock with LZ4, which can cut its size down to nearly
half. Of course, masked ROMs usually don't come with decompression
algorithms built in, so we need to introduce a little decompression stub
that can decompress the rest of the bootblock. This is done by creating
a new "decompressor" stage which runs before the bootblock, but includes
the compressed bootblock code in its data section. It needs to be as
small as possible to get a real benefit from this approach, which means
no device drivers, no console output, no exception handling, etc.
Besides the decompression algorithm itself we only include the timer
driver so that we can measure the boot speed impact of decompression. On
ARM and ARM64 systems, we also need to give SoC code a chance to
initialize the MMU, since running decompression without MMU is
prohibitively slow on these architectures.
This feature is implemented for ARM and ARM64 architectures for now,
although most of it is architecture-independent and it should be
relatively simple to port to other platforms where a masked ROM loads
the bootblock into SRAM. It is also supposed to be a clean starting
point from which later optimizations can hopefully cut down the
decompression stub size (currently ~4K on RK3399) a bit more.
NOTE: Bootblock compression is not for everyone. Possible side effects
include trying to run LZ4 on CPUs that come out of reset extremely
underclocked or enabling this too early in SoC bring-up and getting
frustrated trying to find issues in an undebuggable environment. Ask
your SoC vendor if bootblock compression is right for you.
Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-16 23:14:04 +02:00
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PROG_BOOTBLOCK,
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2018-05-21 20:30:17 +02:00
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PROG_VERSTAGE,
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PROG_ROMSTAGE,
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PROG_RAMSTAGE,
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PROG_REFCODE,
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PROG_PAYLOAD,
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PROG_BL31,
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PROG_BL32,
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2018-11-08 10:39:39 +01:00
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PROG_POSTCAR,
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2019-07-07 13:10:56 +02:00
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PROG_OPENSBI,
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2015-12-08 21:34:35 +01:00
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};
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2016-03-31 20:49:00 +02:00
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/*
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* prog_segment_loaded() is called for each segment of a program loaded. The
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* SEG_FINAL flag will be set on the last segment loaded. The following two
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* functions, platform_segment_loaded() and arch_segment_loaded(), are called
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* in that order within prog_segment_loaded(). In short, rely on
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* prog_segment_loaded() to perform the proper dispatch sequence.
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*/
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void prog_segment_loaded(uintptr_t start, size_t size, int flags);
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void platform_segment_loaded(uintptr_t start, size_t size, int flags);
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2015-03-20 15:42:05 +01:00
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void arch_segment_loaded(uintptr_t start, size_t size, int flags);
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2015-01-09 14:14:20 +01:00
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2015-03-20 19:00:20 +01:00
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/* Representation of a program. */
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struct prog {
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2015-12-08 21:34:35 +01:00
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/* The region_device is the source of program content to load. After
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* loading program it represents the memory region of the stages and
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* payload. For architectures that use a bounce buffer
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2015-05-20 19:08:55 +02:00
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* then it would represent the bounce buffer. */
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2015-12-08 21:34:35 +01:00
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enum prog_type type;
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2018-05-03 10:35:26 +02:00
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uint32_t cbfs_type;
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2015-12-08 21:34:35 +01:00
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const char *name;
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struct region_device rdev;
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2015-03-20 19:00:20 +01:00
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/* Entry to program with optional argument. It's up to the architecture
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* to decide if argument is passed. */
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void (*entry)(void *);
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void *arg;
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};
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2015-05-20 19:08:55 +02:00
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#define PROG_INIT(type_, name_) \
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{ \
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2015-12-08 21:34:35 +01:00
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.type = (type_), \
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.name = (name_), \
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2015-05-20 19:08:55 +02:00
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}
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static inline const char *prog_name(const struct prog *prog)
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{
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2015-12-08 21:34:35 +01:00
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return prog->name;
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2015-05-20 19:08:55 +02:00
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}
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2015-12-08 21:34:35 +01:00
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static inline enum prog_type prog_type(const struct prog *prog)
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2015-05-20 19:08:55 +02:00
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{
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2015-12-08 21:34:35 +01:00
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return prog->type;
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2015-05-20 19:08:55 +02:00
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}
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2018-05-03 10:35:26 +02:00
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static inline uint32_t prog_cbfs_type(const struct prog *prog)
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{
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return prog->cbfs_type;
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}
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2015-05-20 19:08:55 +02:00
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static inline struct region_device *prog_rdev(struct prog *prog)
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{
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2015-12-08 21:34:35 +01:00
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return &prog->rdev;
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2015-05-20 19:08:55 +02:00
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}
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2015-05-19 23:25:20 +02:00
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/* Only valid for loaded programs. */
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2015-03-20 19:00:20 +01:00
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static inline size_t prog_size(const struct prog *prog)
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{
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2015-12-08 21:34:35 +01:00
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return region_device_sz(&prog->rdev);
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2015-03-20 19:00:20 +01:00
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}
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2015-05-19 23:25:20 +02:00
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/* Only valid for loaded programs. */
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2015-03-20 19:00:20 +01:00
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static inline void *prog_start(const struct prog *prog)
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{
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2015-12-08 21:34:35 +01:00
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return rdev_mmap_full(&prog->rdev);
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2015-03-20 19:00:20 +01:00
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}
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static inline void *prog_entry(const struct prog *prog)
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{
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return prog->entry;
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}
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static inline void *prog_entry_arg(const struct prog *prog)
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{
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return prog->arg;
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}
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2015-05-19 23:25:20 +02:00
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/* region_device representing the 32-bit flat address space. */
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extern const struct mem_region_device addrspace_32bit;
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static inline void prog_memory_init(struct prog *prog, uintptr_t ptr,
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size_t size)
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{
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2015-12-08 21:34:35 +01:00
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rdev_chain(&prog->rdev, &addrspace_32bit.rdev, ptr, size);
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2015-05-19 23:25:20 +02:00
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}
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2015-03-20 19:00:20 +01:00
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static inline void prog_set_area(struct prog *prog, void *start, size_t size)
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{
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2015-05-19 23:25:20 +02:00
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prog_memory_init(prog, (uintptr_t)start, size);
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2015-03-20 19:00:20 +01:00
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}
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static inline void prog_set_entry(struct prog *prog, void *e, void *arg)
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{
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prog->entry = e;
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prog->arg = arg;
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}
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2019-10-23 17:07:15 +02:00
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static inline void prog_set_arg(struct prog *prog, void *arg)
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{
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prog->arg = arg;
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}
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2015-05-16 06:39:23 +02:00
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/* Locate the identified program to run. Return 0 on success. < 0 on error. */
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2015-12-09 00:00:23 +01:00
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int prog_locate(struct prog *prog);
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2019-06-14 14:36:37 +02:00
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/* The prog_locate_hook() is called prior to CBFS traversal. The hook can be
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* used to implement policy that allows or prohibits further progress through
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* prog_locate(). The type and name field within struct prog are the only valid
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* fields. A 0 return value allows further progress while a non-zero return
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* value prohibits further progress */
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int prog_locate_hook(struct prog *prog);
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2015-05-20 19:08:55 +02:00
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2015-03-20 21:55:08 +01:00
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/* Run the program described by prog. */
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void prog_run(struct prog *prog);
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/* Per architecture implementation running a program. */
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void arch_prog_run(struct prog *prog);
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/* Platform (SoC/chipset) specific overrides for running a program. This is
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* called prior to calling the arch_prog_run. Thus, if there is anything
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* special that needs to be done by the platform similar to the architecture
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* code it needs to that as well. */
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void platform_prog_run(struct prog *prog);
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2015-03-20 22:37:12 +01:00
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struct prog_loader_ops {
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const char *name;
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2015-04-28 22:59:12 +02:00
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/* Determine if the loader is the active one. If so returns 1 else 0
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* or < 0 on error. */
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int (*is_loader_active)(struct prog *prog);
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2015-05-16 06:39:23 +02:00
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/* Returns < 0 on error or 0 on success. This function locates
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* the rdev representing the file data associated with the passed in
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* prog. */
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int (*locate)(struct prog *prog);
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2015-03-20 22:37:12 +01:00
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};
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2015-03-17 19:17:06 +01:00
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/************************
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* ROMSTAGE LOADING *
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************************/
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/* Run romstage from bootblock. */
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void run_romstage(void);
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2015-03-17 17:43:44 +01:00
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/************************
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* RAMSTAGE LOADING *
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************************/
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2015-03-20 22:37:12 +01:00
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/* Run ramstage from romstage. */
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void run_ramstage(void);
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2016-06-28 06:38:46 +02:00
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/* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path,
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* if ramstage overwrites low memory. */
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void backup_ramstage_section(uintptr_t base, size_t size);
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2015-03-17 17:43:44 +01:00
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/***********************
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* PAYLOAD LOADING *
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***********************/
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2018-06-07 05:31:43 +02:00
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int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size);
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2015-03-20 16:20:15 +01:00
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/* Load payload into memory in preparation to run. */
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void payload_load(void);
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2014-02-24 21:56:34 +01:00
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/* Run the loaded payload. */
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2015-03-20 16:20:15 +01:00
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void payload_run(void);
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2014-02-24 21:56:34 +01:00
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2014-02-26 03:36:56 +01:00
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/* Mirror the payload to be loaded. */
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2015-03-20 22:37:12 +01:00
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void mirror_payload(struct prog *payload);
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2014-02-24 21:56:34 +01:00
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arm64: Use 'payload' format for ATF instead of 'stage'
Switch the BL31 (ARM Trusted Firmware) format to payload so that it can
have multiple independent segments. This also requires disabling the region
check since SRAM is currently faulted by that check.
This has been tested with Rockchip's pending change:
https://chromium-review.googlesource.com/#/c/368592/3
with the patch mentioned on the bug at #13.
BUG=chrome-os-partner:56314
BRANCH=none
TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is
correct though:
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 1b440 size 15a75
Loading segment from ROM address 0x0000000000100000
code (compression=1)
New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d
Loading segment from ROM address 0x000000000010001c
Entry Point 0x0000000018104800
Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
using LZMA
[ 0x18104800, 18137d90, 0x192843e0) <- 00100038
Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650
dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1
Jumping to boot code at 0000000018104800(00000000f7eda000)
CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes
CBFS: 'VBOOT' located CBFS at [402000:44cc00)
CBFS: Locating 'fallback/bl31'
CBFS: Found @ offset 10ec0 size 8d0c
Loading segment from ROM address 0x0000000000100000
code (compression=1)
New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192
Loading segment from ROM address 0x000000000010001c
code (compression=1)
New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26
Loading segment from ROM address 0x0000000000100038
Entry Point 0x0000000000010000
Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
using LZMA
[ 0x00010000, 00035708, 0x00050000) <- 00100054
Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8
dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff
Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
using LZMA
[ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6
dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff
Loaded segments
INFO: plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80
INFO: plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364
INFO: plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648
NOTICE: BL31: v1.2(debug):
NOTICE: BL31: Built : Sun Sep 4 22:36:16 UTC 2016
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO: plat_rockchip_pmu_init(1189): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x18104800
INFO: SPSR = 0x8
Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e
Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376849
Original-Commit-Ready: Simon Glass <sjg@google.com>
Original-Tested-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16706
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-27 20:18:38 +02:00
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/*
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2018-10-25 00:46:51 +02:00
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* selfload() and selfload_check() load payloads into memory.
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* selfload() does not check the payload to see if it targets memory.
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* Call selfload_check() to check that the payload targets usable memory.
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* If it does not, the load will fail and this function
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* will return false. On successful payload loading these functions return true.
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arm64: Use 'payload' format for ATF instead of 'stage'
Switch the BL31 (ARM Trusted Firmware) format to payload so that it can
have multiple independent segments. This also requires disabling the region
check since SRAM is currently faulted by that check.
This has been tested with Rockchip's pending change:
https://chromium-review.googlesource.com/#/c/368592/3
with the patch mentioned on the bug at #13.
BUG=chrome-os-partner:56314
BRANCH=none
TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is
correct though:
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 1b440 size 15a75
Loading segment from ROM address 0x0000000000100000
code (compression=1)
New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d
Loading segment from ROM address 0x000000000010001c
Entry Point 0x0000000018104800
Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
using LZMA
[ 0x18104800, 18137d90, 0x192843e0) <- 00100038
Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650
dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1
Jumping to boot code at 0000000018104800(00000000f7eda000)
CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes
CBFS: 'VBOOT' located CBFS at [402000:44cc00)
CBFS: Locating 'fallback/bl31'
CBFS: Found @ offset 10ec0 size 8d0c
Loading segment from ROM address 0x0000000000100000
code (compression=1)
New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192
Loading segment from ROM address 0x000000000010001c
code (compression=1)
New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26
Loading segment from ROM address 0x0000000000100038
Entry Point 0x0000000000010000
Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
using LZMA
[ 0x00010000, 00035708, 0x00050000) <- 00100054
Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8
dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff
Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
using LZMA
[ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6
dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff
Loaded segments
INFO: plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80
INFO: plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364
INFO: plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648
NOTICE: BL31: v1.2(debug):
NOTICE: BL31: Built : Sun Sep 4 22:36:16 UTC 2016
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO: plat_rockchip_pmu_init(1189): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x18104800
INFO: SPSR = 0x8
Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e
Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376849
Original-Commit-Ready: Simon Glass <sjg@google.com>
Original-Tested-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16706
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-27 20:18:38 +02:00
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*
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* Defined in src/lib/selfboot.c
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*/
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2019-01-28 10:22:22 +01:00
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bool selfload_check(struct prog *payload, enum bootmem_type dest_type);
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2018-10-25 00:46:51 +02:00
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bool selfload(struct prog *payload);
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2015-03-17 17:43:44 +01:00
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#endif /* PROGRAM_LOADING_H */
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