364 lines
10 KiB
C
364 lines
10 KiB
C
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/*
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* Copyright (c) 2014 Chromium OS authors
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*/
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#include <libpayload.h>
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enum IPQ_UART_DM_PARITY_MODE {
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IPQ_UART_DM_NO_PARITY,
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IPQ_UART_DM_ODD_PARITY,
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IPQ_UART_DM_EVEN_PARITY,
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IPQ_UART_DM_SPACE_PARITY
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};
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/* UART Stop Bit Length */
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enum IPQ_UART_DM_STOP_BIT_LEN {
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IPQ_UART_DM_SBL_9_16,
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IPQ_UART_DM_SBL_1,
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IPQ_UART_DM_SBL_1_9_16,
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IPQ_UART_DM_SBL_2
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};
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/* UART Bits per Char */
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enum IPQ_UART_DM_BITS_PER_CHAR {
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IPQ_UART_DM_5_BPS,
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IPQ_UART_DM_6_BPS,
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IPQ_UART_DM_7_BPS,
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IPQ_UART_DM_8_BPS
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};
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#define IPQ_UART_DM_CR(base) (((u8 *)(base)) + 0x10)
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#define IPQ_UART_DM_DMEN(base) (((u8 *)(base)) + 0x3C)
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#define IPQ_UART_DM_DMRX(base) (((u8 *)(base)) + 0x34)
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#define IPQ_UART_DM_HCR(base) (((u8 *)(base)) + 0x24)
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#define IPQ_UART_DM_IMR(base) (((u8 *)(base)) + 0x14)
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#define IPQ_UART_DM_IPR(base) (((u8 *)(base)) + 0x18)
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#define IPQ_UART_DM_IRDA(base) (((u8 *)(base)) + 0x38)
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#define IPQ_UART_DM_MISR(base) (((u8 *)(base)) + 0x10)
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#define IPQ_UART_DM_MR1(base) (((u8 *)(base)) + 0x00)
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#define IPQ_UART_DM_MR2(base) (((u8 *)(base)) + 0x04)
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#define IPQ_UART_DM_NO_CHARS_FOR_TX(base) (((u8 *)(base)) + 0x040)
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#define IPQ_UART_DM_RF(base, x) (((u8 *)(base)) + 0x70 + 4*(x))
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#define IPQ_UART_DM_RFWR(base) (((u8 *)(base)) + 0x20)
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#define IPQ_UART_DM_RX_TOTAL_SNAP(base) (((u8 *)(base)) + 0x38)
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#define IPQ_UART_DM_SR(base) (((u8 *)(base)) + 0x008)
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#define IPQ_UART_DM_TF(base, x) (((u8 *)(base)) + 0x70 + 4*(x))
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#define IPQ_UART_DM_TFWR(base) (((u8 *)(base)) + 0x1C)
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#define IPQ_UART_DM_TXLEV (1 << 0)
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#define IPQ_UART_DM_TX_READY (1 << 7)
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#define IPQ_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
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#define IPQ_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 )
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#define IPQ_UART_DM_CR_CH_CMD(x) (IPQ_UART_DM_CR_CH_CMD_LSB(x)\
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| IPQ_UART_DM_CR_CH_CMD_MSB(x))
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#define IPQ_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
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#define IPQ_UART_DM_8_N_1_MODE (IPQ_UART_DM_NO_PARITY | \
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(IPQ_UART_DM_SBL_1 << 2) | \
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(IPQ_UART_DM_8_BPS << 4))
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#define IPQ_UART_DM_CR_RX_ENABLE (1 << 0)
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#define IPQ_UART_DM_CR_TX_ENABLE (1 << 2)
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#define IPQ_UART_DM_CMD_RESET_RX IPQ_UART_DM_CR_CH_CMD(1)
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#define IPQ_UART_DM_CMD_RESET_TX IPQ_UART_DM_CR_CH_CMD(2)
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#define IPQ_UART_DM_CMD_RESET_ERR_STAT IPQ_UART_DM_CR_CH_CMD(3)
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#define IPQ_UART_DM_CMD_RES_STALE_INT IPQ_UART_DM_CR_CH_CMD(8)
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#define IPQ_UART_DM_CMD_RES_TX_ERR IPQ_UART_DM_CR_CH_CMD(10)
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#define IPQ_UART_DM_GCMD_ENA_STALE_EVT IPQ_UART_DM_CR_GENERAL_CMD(5)
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#define IPQ_UART_DM_RXSTALE (1 << 3)
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#define IPQ_UART_DM_IMR_ENABLED (IPQ_UART_DM_TX_READY | \
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IPQ_UART_DM_TXLEV | \
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IPQ_UART_DM_RXSTALE)
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#define IPQ_UART_DM_TFW_VALUE 0
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#define IPQ_UART_DM_RFW_VALUE 1
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#define IPQ_UART_DM_DMRX_DEF_VALUE 0x220
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#define IPQ_UART_DM_SR_TXEMT (1 << 3)
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#define IPQ_UART_DM_SR_UART_OVERRUN (1 << 4)
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#define IPQ_UART_DM_E_SUCCESS 0
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#define IPQ_UART_DM_E_INVAL 3
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#define IPQ_UART_DM_E_RX_NOT_READY 5
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#define IPQ_UART_DM_STALE_TIMEOUT_LSB 0x0f
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static struct console_input_driver consin = {};
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static struct console_output_driver consout = {};
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#define FIFO_DATA_SIZE 4
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static void *base_uart_addr;
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/*
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* All constants lifted from u-boot's
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* board/qcom/ipq806x_cdp/ipq806x_board_param.h
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*/
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static unsigned int msm_boot_uart_dm_init(void *uart_dm_base);
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/* Number of pending received characters */
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static int uart_ready_data_count;
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/* Received data as it came from 32 bit wide FIFO */
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static unsigned int uart_rx_fifo_word;
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/**
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* msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
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* @uart_dm_base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
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{
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/* Reset receiver */
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writel(IPQ_UART_DM_CMD_RESET_RX,
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IPQ_UART_DM_CR(uart_dm_base));
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/* Enable receiver */
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writel(IPQ_UART_DM_CR_RX_ENABLE,
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IPQ_UART_DM_CR(uart_dm_base));
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writel(IPQ_UART_DM_DMRX_DEF_VALUE,
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IPQ_UART_DM_DMRX(uart_dm_base));
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/* Clear stale event */
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writel(IPQ_UART_DM_CMD_RES_STALE_INT,
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IPQ_UART_DM_CR(uart_dm_base));
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/* Enable stale event */
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writel(IPQ_UART_DM_GCMD_ENA_STALE_EVT,
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IPQ_UART_DM_CR(uart_dm_base));
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return IPQ_UART_DM_E_SUCCESS;
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}
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/**
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* Reads a word from the RX FIFO or returns not ready.
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*/
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static unsigned msm_boot_uart_dm_read(void)
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{
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static int total_rx_data = 0;
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static int rx_data_read = 0;
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void *base = base_uart_addr;
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uint32_t status_reg;
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/* RXSTALE means RX FIFO is not empty. */
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status_reg = readl(IPQ_UART_DM_MISR(base));
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if (!(status_reg & IPQ_UART_DM_RXSTALE))
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return IPQ_UART_DM_E_RX_NOT_READY;
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/* Check for Overrun error. We'll just reset Error Status */
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if (readl(IPQ_UART_DM_SR(base)) &
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IPQ_UART_DM_SR_UART_OVERRUN) {
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writel(IPQ_UART_DM_CMD_RESET_ERR_STAT,
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IPQ_UART_DM_CR(base));
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total_rx_data = rx_data_read = 0;
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msm_boot_uart_dm_init(base);
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return IPQ_UART_DM_E_RX_NOT_READY;
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}
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/* Clear stale event. */
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writel(IPQ_UART_DM_CMD_RES_STALE_INT, IPQ_UART_DM_CR(base));
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/* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
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if (total_rx_data == 0)
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total_rx_data = readl(IPQ_UART_DM_RX_TOTAL_SNAP(base));
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/* Data available in FIFO; read a word. */
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uart_rx_fifo_word = readl(IPQ_UART_DM_RF(base, 0));
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/*
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* TODO(vbendeb): this is wrong and will be addressed shortly: there
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* should be no zeros returned from the FIFO in case there are
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* received characters (we don't expect to be receiving zeros).
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* See http://crosbug.com/p/29313
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*/
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if (uart_rx_fifo_word == 0) {
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return IPQ_UART_DM_E_RX_NOT_READY;
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}
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/* increment the total count of chars we've read so far */
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rx_data_read += FIFO_DATA_SIZE;
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/* Actual count of valid data in word */
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uart_ready_data_count =
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((total_rx_data < rx_data_read) ?
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(FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) :
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FIFO_DATA_SIZE);
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/* If there are still data left in FIFO we'll read them before
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* initializing RX Transfer again
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*/
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if (rx_data_read < total_rx_data)
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return IPQ_UART_DM_E_SUCCESS;
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msm_boot_uart_dm_init_rx_transfer(base);
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total_rx_data = rx_data_read = 0;
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return IPQ_UART_DM_E_SUCCESS;
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}
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void serial_putchar(unsigned data)
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{
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int num_of_chars = 0;
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unsigned tx_data = 0;
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void *base = base_uart_addr;
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if (data == '\n') {
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num_of_chars++;
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tx_data = '\r';
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}
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tx_data |= data << (8 * num_of_chars++);
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/* Wait until transmit FIFO is empty. */
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while (!(readl(IPQ_UART_DM_SR(base)) &
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IPQ_UART_DM_SR_TXEMT))
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udelay(1);
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/*
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* TX FIFO is ready to accept new character(s). First write number of
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* characters to be transmitted.
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*/
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writel(num_of_chars, IPQ_UART_DM_NO_CHARS_FOR_TX(base));
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/* And now write the character(s) */
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writel(tx_data, IPQ_UART_DM_TF(base, 0));
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}
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/*
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* msm_boot_uart_dm_reset - resets UART controller
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* @base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_reset(void *base)
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{
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writel(IPQ_UART_DM_CMD_RESET_RX, IPQ_UART_DM_CR(base));
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writel(IPQ_UART_DM_CMD_RESET_TX, IPQ_UART_DM_CR(base));
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writel(IPQ_UART_DM_CMD_RESET_ERR_STAT,
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IPQ_UART_DM_CR(base));
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writel(IPQ_UART_DM_CMD_RES_TX_ERR, IPQ_UART_DM_CR(base));
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writel(IPQ_UART_DM_CMD_RES_STALE_INT, IPQ_UART_DM_CR(base));
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return IPQ_UART_DM_E_SUCCESS;
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}
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/*
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* msm_boot_uart_dm_init - initilaizes UART controller
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* @uart_dm_base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_init(void *uart_dm_base)
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{
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/* Configure UART mode registers MR1 and MR2 */
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/* Hardware flow control isn't supported */
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writel(0x0, IPQ_UART_DM_MR1(uart_dm_base));
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/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
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writel(IPQ_UART_DM_8_N_1_MODE,
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IPQ_UART_DM_MR2(uart_dm_base));
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/* Configure Interrupt Mask register IMR */
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writel(IPQ_UART_DM_IMR_ENABLED,
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IPQ_UART_DM_IMR(uart_dm_base));
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/*
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* Configure Tx and Rx watermarks configuration registers
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* TX watermark value is set to 0 - interrupt is generated when
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* FIFO level is less than or equal to 0
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*/
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writel(IPQ_UART_DM_TFW_VALUE,
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IPQ_UART_DM_TFWR(uart_dm_base));
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/* RX watermark value */
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writel(IPQ_UART_DM_RFW_VALUE,
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IPQ_UART_DM_RFWR(uart_dm_base));
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/* Configure Interrupt Programming Register */
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/* Set initial Stale timeout value */
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writel(IPQ_UART_DM_STALE_TIMEOUT_LSB,
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IPQ_UART_DM_IPR(uart_dm_base));
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/* Configure IRDA if required */
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/* Disabling IRDA mode */
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writel(0x0, IPQ_UART_DM_IRDA(uart_dm_base));
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/* Configure hunt character value in HCR register */
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/* Keep it in reset state */
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writel(0x0, IPQ_UART_DM_HCR(uart_dm_base));
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/*
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* Configure Rx FIFO base address
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* Both TX/RX shares same SRAM and default is half-n-half.
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* Sticking with default value now.
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* As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
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* We have found RAM_ADDR_WIDTH = 0x7f
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*/
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/* Issue soft reset command */
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msm_boot_uart_dm_reset(uart_dm_base);
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/* Enable/Disable Rx/Tx DM interfaces */
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/* Data Mover not currently utilized. */
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writel(0, IPQ_UART_DM_DMEN(uart_dm_base));
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/* Enable transmitter */
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writel(IPQ_UART_DM_CR_TX_ENABLE,
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IPQ_UART_DM_CR(uart_dm_base));
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/* Initialize Receive Path */
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msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
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return 0;
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}
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/**
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* serial_havechar - checks if data available for reading
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*
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* Returns 1 if data available, 0 otherwise
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*/
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int serial_havechar(void)
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{
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/* Return if data is already read */
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if (uart_ready_data_count)
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return 1;
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/* Read data from the FIFO */
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if (msm_boot_uart_dm_read() != IPQ_UART_DM_E_SUCCESS)
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return 0;
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return 1;
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}
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/**
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* ipq806x_serial_getc - reads a character
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*
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* Returns the character read from serial port.
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*/
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int serial_getchar(void)
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{
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uint8_t byte;
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while (!serial_havechar()) {
|
||
|
|
/* wait for incoming data */
|
||
|
|
}
|
||
|
|
|
||
|
|
byte = (uint8_t)(uart_rx_fifo_word & 0xff);
|
||
|
|
uart_rx_fifo_word = uart_rx_fifo_word >> 8;
|
||
|
|
uart_ready_data_count--;
|
||
|
|
|
||
|
|
return byte;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* For simplicity sake let's rely on coreboot initalizing the UART. */
|
||
|
|
void serial_console_init(void)
|
||
|
|
{
|
||
|
|
struct cb_serial *sc_ptr = lib_sysinfo.serial;
|
||
|
|
|
||
|
|
if (!sc_ptr)
|
||
|
|
return;
|
||
|
|
|
||
|
|
base_uart_addr = (void *) sc_ptr->baseaddr;
|
||
|
|
|
||
|
|
consin.havekey = serial_havechar;
|
||
|
|
consin.getchar = serial_getchar;
|
||
|
|
|
||
|
|
consout.putchar = serial_putchar;
|
||
|
|
|
||
|
|
console_add_output_driver(&consout);
|
||
|
|
console_add_input_driver(&consin);
|
||
|
|
}
|