2022-09-21 17:06:15 +02:00
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# Driver Devicetree Entries
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Let's take a look at an example entry from
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``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
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```
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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2022-09-06 22:32:59 +02:00
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
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2022-09-21 17:33:22 +02:00
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register "detect" = "1"
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2022-09-21 17:06:15 +02:00
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register "wake" = "GPE0_DW0_21"
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device i2c 15 on end
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end
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end # I2C #0
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```
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When this entry is processed during ramstage, it will create a device in the
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ACPI SSDT table (all devices in devicetrees end up in the SSDT table). The ACPI
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generation routines in coreboot actually generate the raw bytecode that
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represents the device's structure, but looking at ASL code is easier to
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understand; see below for what the disassembled bytecode looks like:
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```
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Scope (\_SB.PCI0.I2C0)
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{
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Device (D015)
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{
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Name (_HID, "ELAN0000") // _HID: Hardware ID
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Name (_UID, Zero) // _UID: Unique ID
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Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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Return (0x0F)
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}
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
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AddressingMode7Bit, "\\_SB.PCI0.I2C0",
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0x00, ResourceConsumer, , Exclusive, )
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2022-09-06 22:32:59 +02:00
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
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2022-09-21 17:06:15 +02:00
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{
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0x0000002D,
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}
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})
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Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT) // _S0W: S0 Device Wake State
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Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
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{
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0x15, // GPE #21
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0x03 // Sleep state S3
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})
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}
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}
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```
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2022-09-06 22:32:59 +02:00
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You can see it generates \_HID, \_UID, \_DDN, \_STA, \_CRS, \_S0W, and \_PRW
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2022-09-21 17:06:15 +02:00
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names/methods in the Device's scope.
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## Utilizing a device driver
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The device driver must be enabled for your build. There will be a CONFIG option
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in the Kconfig file in the directory that the driver is in (e.g.,
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``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
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CONFIG_DRIVERS_I2C_GENERIC). The config option will need to be added to your
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mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
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to be compiled into your build.
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## Diving into the above example:
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Let's take a look at how the devicetree language corresponds to the generated
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ASL.
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First, note this:
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```
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chip drivers/i2c/generic
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```
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This means that the device driver we're using has a corresponding structure,
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located at ``src/drivers/i2c/generic/chip.h``, named **struct
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drivers_i2c_generic_config** and it contains many properties you can specify to
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be included in the ACPI table.
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### hid
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```
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register "hid" = ""ELAN0000""
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```
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2022-09-06 22:32:59 +02:00
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This corresponds to **const char \*hid** in the struct. In the ACPI ASL, it
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2022-09-21 17:06:15 +02:00
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translates to:
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```
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Name (_HID, "ELAN0000") // _HID: Hardware ID
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```
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under the device. **This property is used to match the device to its driver
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during enumeration in the OS.**
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### desc
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```
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register "desc" = ""ELAN Touchpad""
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```
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2022-09-06 22:32:59 +02:00
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corresponds to **const char \*desc** and in ASL:
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2022-09-21 17:06:15 +02:00
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```
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Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
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```
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### irq
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It also adds the interrupt,
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```
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2022-09-06 22:32:59 +02:00
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
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2022-09-21 17:06:15 +02:00
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{
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0x0000002D,
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}
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```
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which comes from:
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```
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2022-09-06 22:32:59 +02:00
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
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2022-09-21 17:06:15 +02:00
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```
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2022-09-06 22:32:59 +02:00
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The IRQ settings control the "Trigger" and "Polarity" settings seen above (level
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means it is a level-triggered interrupt as opposed to
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edge-triggered; active low means the interrupt is triggered when the signal is
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low).
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2022-09-21 17:06:15 +02:00
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2022-09-06 22:32:59 +02:00
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Also note that the IRQ names are SoC-specific, and you will need to
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2022-09-21 17:06:15 +02:00
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find the names in your SoC's header file. The ACPI_* macros are defined in
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``src/arch/x86/include/acpi/acpi_device.h``.
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Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
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This is often done in a mainboard-specific file named ``gpio.c``.
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2022-09-06 22:32:59 +02:00
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AMD platforms don't have the ability to route GPIOs to the IO-APIC. Instead the
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GPIO controller needs to be used directly. You can do this by setting the
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`irq_gpio` register and using the `ACPI_GPIO_IRQ_X_X` macros.
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i.e.,
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```
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
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```
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2022-09-21 17:33:22 +02:00
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### detect
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The next register is:
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```
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register "detect" = "1"
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```
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This flag tells the I2C driver that it should attempt to detect the presence of
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the device (using an I2C zero-byte write), and only generate a SSDT entry if the
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device is actually present. This alleviates the OS from having to determine if
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a device is present or not (ChromeOS/Linux) and prevents resource conflict/
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driver issues (Windows).
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Currently, the detect feature works and is hooked up for all I2C touchpads,
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and should be used any time a board has multiple touchpad options.
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I2C audio devices should also work without issue.
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Touchscreens can use this feature as well, but special care is needed to
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implement the proper power sequencing for the device to be detected. Generally,
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this means driving the enable GPIO high and holding the reset GPIO low in early
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2022-11-03 18:43:01 +01:00
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GPIO init (bootblock/romstage), then releasing reset in ramstage. The first
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mainboards in the tree to implement this are google/skyrim and google/guybrush.
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This feature has also been used in downstream forks without issue for some time
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now on several other boards.
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2022-09-21 17:33:22 +02:00
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2022-09-21 17:06:15 +02:00
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### wake
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The last register is:
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```
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register "wake" = "GPE0_DW0_21"
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```
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which indicates that the method of waking the system using the touchpad will be
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through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
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this example. The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
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elsewhere in the devicetree.
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2022-09-06 22:32:59 +02:00
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### device
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2022-09-21 17:06:15 +02:00
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The last bit of the definition of that device includes:
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```
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device i2c 15 on end
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```
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which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
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meaning it will be exposed in the ACPI table. The PCI device that the
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controller is located in determines which I2C bus the device is expected to be
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found on. In this example, this is I2C bus 0. This also determines the ACPI
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"Scope" that the device names and methods will live under, in this case
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"\_SB.PCI0.I2C0".
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2022-09-06 22:32:59 +02:00
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## Wake sources
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The ACPI spec defines two methods to describe how a device can wake the system.
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Only one of these methods should be used, otherwise duplicate wake events will
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be generated.
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### Using GPEs as a wake source
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The `wake` property specified above is used to tell the ACPI subsystem that the
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device can use a GPE to wake the system. The OS can control whether to enable
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or disable the wake source by unmasking/masking off the GPE.
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The `GPIO` -> `GPE` mapping must be configured in firmware. On AMD platforms this is
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generally done by a mainboard specific `gpio.c` file that defines the GPIO
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using `PAD_SCI`. The `GPIO` -> `GPE` mapping is returned by the
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`soc_get_gpio_event_table` method that is defined in the SoC specific `gpio.c`
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file. On Intel platforms, you fill in the `pmc_gpe0_dw0`, `pmc_gpe0_dw1`, and
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`pmc_gpe0_dw2` fields in the devicetree to map 3 GPIO communities to `tier-1`
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GPEs (the rest are available as `tier-2` GPEs).
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Windows has a large caveat when using this method. If you use the `gpio_irq`
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property to define a `GpioInt` in the `_CRS`, and then use the `wake` property
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to define a `GPE`, Windows will
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[BSOD](https://github.com/MicrosoftDocs/windows-driver-docs/blob/staging/windows-driver-docs-pr/debugger/bug-check-0xa5--acpi-bios-error.md)
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complaining about an invalid ACPI configuration.
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> 0x1000D - A device used both GPE and GPIO interrupts, which is not supported.
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In order to avoid this error, you should use the `irq` property instead. AMD
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platforms don't support routing GPIOs to the IO-APIC, so this workaround isn't
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feasible. The other option is to use a wake capable GPIO as described below.
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### Using GPIO interrupts as a wake source
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The `ACPI_IRQ_WAKE_{EDGE,LEVEL}_{LOW,HIGH}` macros can be used when setting the
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`irq` or `gpio_irq` properties. This ends up setting `ExclusiveAndWake` or
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`SharedAndWake` on the `Interrupt` or `GpioInt` ACPI resource.
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This method has a few caveats:
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* On Intel and AMD platforms the IO-APIC can't wake the system. This means using
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the `ACPI_IRQ_WAKE_*` macros with the `irq` property won't actually wake the
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system. Instead you need to use the `gpio_irq` property, or a `GPE` as
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described above.
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* The OS needs to know how to enable the `wake` bit on the GPIO. For linux this
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means the platform specific GPIO controller driver must implement the
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`irq_set_wake` callback. For AMD systems this wasn't
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[implemented](https://github.com/torvalds/linux/commit/d62bd5ce12d79bcd6a6c3e4381daa7375dc21158)
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until linux v5.15. If the controller doesn't define this callback, it's
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possible for the firmware to manually set the `wake` bit on the GPIO. This is
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often done in a mainboard-specific file named `gpio.c`. This is not
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recommended because then it's not possible for the OS to disable the wake
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source.
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* As of
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[linux v6.0-rc5](https://github.com/torvalds/linux/releases/tag/v6.0-rc5),
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the ACPI subsystem doesn't take the interrupt `wake` bit into account when
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deciding on which power state to put the device in before suspending the
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system. This means that if you define a power resource for a device via
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`has_power_resource`, `enable_gpio`, etc, then the linux kernel will place the
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device into D3Cold. i.e., power off the device.
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2022-09-21 17:06:15 +02:00
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## Other auto-generated names
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(see [ACPI specification
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6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
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for more details on ACPI methods)
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### _S0W (S0 Device Wake State)
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2022-09-06 22:32:59 +02:00
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\_S0W indicates the deepest S0 sleep state this device can wake itself from,
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which in this case is `ACPI_DEVICE_SLEEP_D3_HOT`, representing _D3hot_.
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D3Hot means the `PR3` power resources are still on and the device is still
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responsive on the bus. For i2c devices this is generally the same state as `D0`.
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2022-09-21 17:06:15 +02:00
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2022-09-06 22:32:59 +02:00
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### \_PRW (Power Resources for Wake)
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\_PRW indicates the power resources and events required for wake. There are no
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2022-09-21 17:06:15 +02:00
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dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
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as well as the deepest sleep state supporting waking the system (3), which is
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S3.
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2022-09-06 22:32:59 +02:00
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### \_STA (Status)
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The \_STA method is generated automatically, and its values, 0xF, indicates the
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2022-09-21 17:06:15 +02:00
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following:
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Bit [0] – Set if the device is present.
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Bit [1] – Set if the device is enabled and decoding its resources.
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|
Bit [2] – Set if the device should be shown in the UI.
|
|
|
|
|
Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
|
|
|
|
|
|
2022-09-06 22:32:59 +02:00
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|
|
### \_CRS (Current resource settings)
|
|
|
|
|
The \_CRS method is generated automatically, as the driver knows it is an I2C
|
2022-09-21 17:06:15 +02:00
|
|
|
|
controller, and so specifies how to configure the controller for proper
|
|
|
|
|
operation with the touchpad.
|
|
|
|
|
|
|
|
|
|
```
|
|
|
|
|
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
|
|
|
|
|
{
|
|
|
|
|
I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
|
|
|
|
|
AddressingMode7Bit, "\\_SB.PCI0.I2C0",
|
|
|
|
|
0x00, ResourceConsumer, , Exclusive, )
|
|
|
|
|
```
|
|
|
|
|
|
|
|
|
|
## Notes
|
|
|
|
|
|
2022-09-21 17:33:22 +02:00
|
|
|
|
- **All device driver entries in devicetrees end up in the SSDT table, and are
|
|
|
|
|
generated in coreboot's ramstage**
|
|
|
|
|
(The lone exception to this rule is i2c touchpads with the 'detect' flag set;
|
|
|
|
|
in this case, devices not present will not be added to the SSDT)
|