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coreboot-kgpe-d16/payloads/libpayload/arch/arm/exception_asm.S

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libpayload: Catch exceptions and print out an error message. Give some indication what happened instead of just crashing. As part of setup, cause an exception and make sure that we get the right one, and that we recover correctly. Hence we have some assurance that if they really happen we can handle them. Built and booted into test payload on Snow. Saw the built in test function worked correctly. Artificially added code which got an exception and saw that the error information prints correctly. Change-Id: I2e0d022f090ee422fb988074fbb197afa2485caa Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2569 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-04 05:52:05 +01:00
/*
* This file is part of the libpayload project.
*
* Copyright 2013 Google Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
arm: Put exception_stack into BSS "Hey guys, I have this awesome idea! How about we put a huge array filled with 0xa5 into the data segment of our uncompressed romstage for no particular reason? Give our SPI driver something to do so it doesn't get too bored, you know?" Guess it pays off to just hexdump our image and sanity-check it top to bottom every once in a while... Also reduces the size because 8K is crazy just to print a bunch of registers (256 bytes ought to be enough for anybody). Old-Change-Id: Icec0a711a1b5140d2ebcd98338ec638a4b6262fa Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176762 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 61c360a1c3f445535c9ff383a389e643cfe4527c) arm: Remove exception_test() The exception_test() mechanism might have been useful when exceptions were first implemented, but now that they are pretty stable it's really not necessary anymore (especially not on every single boot in production Chromebooks). It forces a simple unaligned access, and as we start having exceptions in stages that might not have paging turned on yet, it's better to remove that completely. Also removed the duplicated implementations of SCTLR-stuff and switched to the existing ones in cache.h. Old-Change-Id: I85e66269f5e2f2dfd3e8aaaa18441493514b62f8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177101 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d0706b848572fbea26e0e432ec5827503b9603c9) Squashed 2 exception related commits. Change-Id: Id2c115ee39a0732c375472afc0194436e2f5e069 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-13 21:49:45 +01:00
.global exception_stack_end
libpayload: Catch exceptions and print out an error message. Give some indication what happened instead of just crashing. As part of setup, cause an exception and make sure that we get the right one, and that we recover correctly. Hence we have some assurance that if they really happen we can handle them. Built and booted into test payload on Snow. Saw the built in test function worked correctly. Artificially added code which got an exception and saw that the error information prints correctly. Change-Id: I2e0d022f090ee422fb988074fbb197afa2485caa Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2569 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-04 05:52:05 +01:00
exception_stack_end:
arm: Put exception_stack into BSS "Hey guys, I have this awesome idea! How about we put a huge array filled with 0xa5 into the data segment of our uncompressed romstage for no particular reason? Give our SPI driver something to do so it doesn't get too bored, you know?" Guess it pays off to just hexdump our image and sanity-check it top to bottom every once in a while... Also reduces the size because 8K is crazy just to print a bunch of registers (256 bytes ought to be enough for anybody). Old-Change-Id: Icec0a711a1b5140d2ebcd98338ec638a4b6262fa Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176762 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 61c360a1c3f445535c9ff383a389e643cfe4527c) arm: Remove exception_test() The exception_test() mechanism might have been useful when exceptions were first implemented, but now that they are pretty stable it's really not necessary anymore (especially not on every single boot in production Chromebooks). It forces a simple unaligned access, and as we start having exceptions in stages that might not have paging turned on yet, it's better to remove that completely. Also removed the duplicated implementations of SCTLR-stuff and switched to the existing ones in cache.h. Old-Change-Id: I85e66269f5e2f2dfd3e8aaaa18441493514b62f8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177101 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d0706b848572fbea26e0e432ec5827503b9603c9) Squashed 2 exception related commits. Change-Id: Id2c115ee39a0732c375472afc0194436e2f5e069 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-13 21:49:45 +01:00
.word 0
libpayload: Catch exceptions and print out an error message. Give some indication what happened instead of just crashing. As part of setup, cause an exception and make sure that we get the right one, and that we recover correctly. Hence we have some assurance that if they really happen we can handle them. Built and booted into test payload on Snow. Saw the built in test function worked correctly. Artificially added code which got an exception and saw that the error information prints correctly. Change-Id: I2e0d022f090ee422fb988074fbb197afa2485caa Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2569 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-04 05:52:05 +01:00
exception_handler:
.word 0
.align 6
.arm
.global exception_table
exception_table:
b 1f
b 2f
b 3f
b 4f
b 5f
b 6f
b 7f
b 8f
1:
ldr sp, _not_used
b exception_common
2:
ldr sp, _undefined_instruction
b exception_common
3:
ldr sp, _software_interrupt
b exception_common
4:
ldr sp, _prefetch_abort
b exception_common
5:
ldr sp, _data_abort
b exception_common
6:
ldr sp, _not_used
b exception_common
7:
ldr sp, _irq
b exception_common
8:
ldr sp, _fiq
b exception_common
exception_common:
str sp, exception_handler
ldr sp, exception_stack_end
push { lr }
armv7: Support stack dump after exceptions This patch enhances the armv7 exception handlers in Coreboot and libpayload to show the correct SP and LR registers from the aborted context, and also dump a part of the current stack. Since we cannot access the banked registers of SVC mode from a different exception mode, it changes Coreboot (and its payloads) to run in System mode instead. As both modes can execute all privileged instructions, this should not have any noticeable effect on firmware operation (please correct me if I'm wrong!). Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6538 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-18 23:39:50 +02:00
stmfd sp, { sp, lr }^
libpayload: Catch exceptions and print out an error message. Give some indication what happened instead of just crashing. As part of setup, cause an exception and make sure that we get the right one, and that we recover correctly. Hence we have some assurance that if they really happen we can handle them. Built and booted into test payload on Snow. Saw the built in test function worked correctly. Artificially added code which got an exception and saw that the error information prints correctly. Change-Id: I2e0d022f090ee422fb988074fbb197afa2485caa Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2569 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-04 05:52:05 +01:00
sub sp, sp, $8
push { r0 - r12 }
mov r0, sp
mov lr, pc
ldr pc, exception_handler
pop { r0 - r12 }
add sp, sp, $8
armv7: Support stack dump after exceptions This patch enhances the armv7 exception handlers in Coreboot and libpayload to show the correct SP and LR registers from the aborted context, and also dump a part of the current stack. Since we cannot access the banked registers of SVC mode from a different exception mode, it changes Coreboot (and its payloads) to run in System mode instead. As both modes can execute all privileged instructions, this should not have any noticeable effect on firmware operation (please correct me if I'm wrong!). Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6538 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-18 23:39:50 +02:00
ldmfd sp!, { pc }^
libpayload: Catch exceptions and print out an error message. Give some indication what happened instead of just crashing. As part of setup, cause an exception and make sure that we get the right one, and that we recover correctly. Hence we have some assurance that if they really happen we can handle them. Built and booted into test payload on Snow. Saw the built in test function worked correctly. Artificially added code which got an exception and saw that the error information prints correctly. Change-Id: I2e0d022f090ee422fb988074fbb197afa2485caa Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2569 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-04 05:52:05 +01:00
_undefined_instruction: .word exception_undefined_instruction
_software_interrupt: .word exception_software_interrupt
_prefetch_abort: .word exception_prefetch_abort
_data_abort: .word exception_data_abort
_not_used: .word exception_not_used
_irq: .word exception_irq
_fiq: .word exception_fiq
.thumb
.global set_vbar
.thumb_func
set_vbar:
mcr p15, 0, r0, c12, c0, 0
bx lr