20 lines
766 B
Markdown
20 lines
766 B
Markdown
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# Cavium bootflow
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The on-chip **BOOTROM** first sets up the L2 cache and the SPI controller.
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It then reads **CSIB_NBL1FW** and **CLIB_NBL1FW** configuration data to get
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the position of the bootstage in flash. It then loads 192KiB from flash into
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L2 cache to a fixed address. The boot mode is called "Non-Secure-Boot" as
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the signature of the bootstage isn't verified.
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The **BOOTROM** can do AES decryption for obfuscation or verify the signature
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of the bootstage. Both features aren't used and won't be described any further.
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* The typical position of bootstage in flash is at address **0x20000**.
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* The entry point in physical DRAM is at address **0x100000**.
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## Layout
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![Bootflow of Cavium CN8xxx SoCs][cavium_bootflow]
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[cavium_bootflow]: cavium_bootflow.png
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