coreboot-kgpe-d16/src/mainboard/siemens/mc_apl1/Makefile.inc

bootblock-y += bootblock.c

# The inclusion of romstage.c is not necessary here.
# It is put down only to the better understanding.
# The file is already included over src/arch/x86/Makefile.inc.
romstage-y += romstage.c
romstage-y += gpio.c

ramstage-y += mainboard.c
ramstage-y += gpio.c
ramstage-y += ptn3460.c
siemens/mc_apl1: Add new mainboard This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MC APL1 mainboard will follow in separate commits. Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Brenton Dong <brenton.m.dong@intel.com> 2017-01-31 15:45:13 +01:00			`bootblock-y += bootblock.c`

siemens/mc_apl1: Clean up the code This patch make some general adaptations in relation to commit 6a489237 (mainboard/intel/leafhill: Clean up). - add necessary defaults to Kconfig - remove irrelevant entries from FMD file - include romstage file for better understanding Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18808 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> 2017-03-14 14:27:29 +01:00			`# The inclusion of romstage.c is not necessary here.`
			`# It is put down only to the better understanding.`
			`# The file is already included over src/arch/x86/Makefile.inc.`
			`romstage-y += romstage.c`
siemens/mc_apl1: Adjust gpio settings Adjust gpio settings according to the hardware layout. Change-Id: I2f440e863c2e6f59298c500ac5aefa3b7386bcdf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18995 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> 2017-03-27 13:25:57 +02:00			`romstage-y += gpio.c`
siemens/mc_apl1: Clean up the code This patch make some general adaptations in relation to commit 6a489237 (mainboard/intel/leafhill: Clean up). - add necessary defaults to Kconfig - remove irrelevant entries from FMD file - include romstage file for better understanding Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18808 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> 2017-03-14 14:27:29 +01:00
siemens/mc_apl1: Add new mainboard This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MC APL1 mainboard will follow in separate commits. Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Brenton Dong <brenton.m.dong@intel.com> 2017-01-31 15:45:13 +01:00			`ramstage-y += mainboard.c`
siemens/mc_apl1: Adjust gpio settings Adjust gpio settings according to the hardware layout. Change-Id: I2f440e863c2e6f59298c500ac5aefa3b7386bcdf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18995 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> 2017-03-27 13:25:57 +02:00			`ramstage-y += gpio.c`
siemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge IC This mainboard uses a LVDS connection for LCD panels. Apollo Lake SoC provides a display controller with three independent pipes (1x eDP and 2x DP/HDMI). PTN3460 is an embedded DisplayPort to LVDS bridge device that enables connectivity between an eDP source and LVDS display panel (http://www.nxp.com/documents/data_sheet/PTN3460.pdf). The bridge contains an On-chip Extended Display Identification Data (EDIT) emulation for EDIT data structures. This patch sets up PTN3460 to be used with the appropriate LCD panel. Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> 2017-03-29 17:09:37 +02:00			`ramstage-y += ptn3460.c`