78 lines
2 KiB
C
78 lines
2 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 - 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef SOC_INTEL_DENVERTON_NS_CHIP_H
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#define SOC_INTEL_DENVERTON_NS_CHIP_H
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struct soc_intel_denverton_ns_config {
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/**
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* Interrupt Routing configuration
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* If bit7 is 1, the interrupt is disabled.
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*/
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uint8_t pirqa_routing;
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uint8_t pirqb_routing;
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uint8_t pirqc_routing;
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uint8_t pirqd_routing;
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uint8_t pirqe_routing;
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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/**
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* Device Interrupt Routing configuration
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* Interrupt Pin x Route.
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* 0h = PIRQA#
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* 1h = PIRQB#
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* 2h = PIRQC#
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* 3h = PIRQD#
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* 4h = PIRQE#
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* 5h = PIRQF#
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* 6h = PIRQG#
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* 7h = PIRQH#
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*/
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uint16_t ir00_routing;
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uint16_t ir01_routing;
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uint16_t ir02_routing;
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uint16_t ir03_routing;
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uint16_t ir04_routing;
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uint16_t ir05_routing;
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uint16_t ir06_routing;
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uint16_t ir07_routing;
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uint16_t ir08_routing;
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uint16_t ir09_routing;
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uint16_t ir10_routing;
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uint16_t ir11_routing;
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uint16_t ir12_routing;
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/**
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* Device Interrupt Polarity Control
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* ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
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* ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
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* ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
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* ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
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*/
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uint32_t ipc0;
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uint32_t ipc1;
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uint32_t ipc2;
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uint32_t ipc3;
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};
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extern struct chip_operations soc_intel_denverton_ns_ops;
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typedef struct soc_intel_denverton_ns_config config_t;
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#endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */
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