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coreboot-kgpe-d16/src/soc/qualcomm/ipq806x/Kconfig

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soc/qualcomm: Add generic support skeleton for ipq806x Skeleton for soc ipq806x Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911) soc/ipq806x: Disable LPAE mode. LPAE (large physical address extension) is not available on this SOC core, do not enable it. Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani <deepad@quicinc.com> (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b) Squashed 2 commits for the Qualcomm ipq806x SOC. Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6963 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2014-03-19 22:29:48 +01:00
config SOC_QC_IPQ806X
select ARCH_BOOTBLOCK_ARMV4
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
bool
default n
if SOC_QC_IPQ806X
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
Include IPQ8064 SBLs code in the coreboot bootblock We want the coreboot build produce an image which can be run on the target, even if the remaining parts of the bootprom (recovery path, read-write stages, gbb, etc.) are not available yet. This is achieved by including the Qualcomm SBLs blob in the bootblock. CQ-DEPEND=CL:193518 BRANCH=None BUG=chrome-os-partner:27784 TEST=manual . run the following commands inside chroot to confirm expected image layout (no actual code is executed on the target yet): $ emerge-storm coreboot $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom 2>/dev/null | head -1 000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom | grep 220000 220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a Original-Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193540 (cherry picked from commit 64e193974ee448f78e0a5775a440094901590afb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idbdbeb9d229eff94a7a94af5dc4844a295458200 Reviewed-on: http://review.coreboot.org/7262 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-04-08 03:59:53 +02:00
default 0x221000
soc/qualcomm: Add generic support skeleton for ipq806x Skeleton for soc ipq806x Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911) soc/ipq806x: Disable LPAE mode. LPAE (large physical address extension) is not available on this SOC core, do not enable it. Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani <deepad@quicinc.com> (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b) Squashed 2 commits for the Qualcomm ipq806x SOC. Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6963 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2014-03-19 22:29:48 +01:00
config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
Include IPQ8064 SBLs code in the coreboot bootblock We want the coreboot build produce an image which can be run on the target, even if the remaining parts of the bootprom (recovery path, read-write stages, gbb, etc.) are not available yet. This is achieved by including the Qualcomm SBLs blob in the bootblock. CQ-DEPEND=CL:193518 BRANCH=None BUG=chrome-os-partner:27784 TEST=manual . run the following commands inside chroot to confirm expected image layout (no actual code is executed on the target yet): $ emerge-storm coreboot $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom 2>/dev/null | head -1 000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom | grep 220000 220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a Original-Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193540 (cherry picked from commit 64e193974ee448f78e0a5775a440094901590afb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idbdbeb9d229eff94a7a94af5dc4844a295458200 Reviewed-on: http://review.coreboot.org/7262 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-04-08 03:59:53 +02:00
default 0x221080
soc/qualcomm: Add generic support skeleton for ipq806x Skeleton for soc ipq806x Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911) soc/ipq806x: Disable LPAE mode. LPAE (large physical address extension) is not available on this SOC core, do not enable it. Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani <deepad@quicinc.com> (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b) Squashed 2 commits for the Qualcomm ipq806x SOC. Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6963 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2014-03-19 22:29:48 +01:00
Provide ability to integrate with QComm SBLs Ipq8064 SBLs initialize the hardware to prepare it to run an arbitrary user provided bootloader. The only bootloader requirements imposed by the SBLs are that it is concatenated with the SBL chunks in the bootprm AND it uses MBN encapsulation (mostly to specify the size and load address). This patch adds configuration options to specify the location of the SBL blobs and to require MBN encapsulation of the bootblock. BRANCH=none BUG=chrome-os-partner:27784 TEST=manual - the below demonstrates added encapsulation, no code run attempts have been made yet: $ FEATURES=noclean emerge-storm coreboot $ cd /build/storm/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999 $ \od -t x4 build/cbfs/fallback/bootblock.bin | head -3 0000000 00000005 00000003 00000000 2a010000 0000020 00000be0 00000be0 2a010be0 00000000 0000040 2a010be0 00000000 e32bf0df e59f0030 Original-Change-Id: Iae30ad08059e2b35c434ac25a410ac2017752957 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193511 (cherry picked from commit bf16ea915c723ab124d817e3b0d950282e3cf1c1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53c71d382ec1d826f530d7afb545f64ec4eaf96b Reviewed-on: http://review.coreboot.org/7261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-04-08 00:26:39 +02:00
config MBN_ENCAPSULATION
depends on USE_BLOBS
bool "bootblock encapsulation for ipq8064"
default y
config SBL_BLOB
depends on USE_BLOBS
string "file name of the Qualcomm SBL blob"
default "3rdparty/cpu/qualcomm/ipq8064/sbls.bin"
help
The path and filename of the binary blob containing
ipq806x early initialization code, as supplied by the
vendor.
config BOOTBLOCK_BASE
Include IPQ8064 SBLs code in the coreboot bootblock We want the coreboot build produce an image which can be run on the target, even if the remaining parts of the bootprom (recovery path, read-write stages, gbb, etc.) are not available yet. This is achieved by including the Qualcomm SBLs blob in the bootblock. CQ-DEPEND=CL:193518 BRANCH=None BUG=chrome-os-partner:27784 TEST=manual . run the following commands inside chroot to confirm expected image layout (no actual code is executed on the target yet): $ emerge-storm coreboot $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom 2>/dev/null | head -1 000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom | grep 220000 220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a Original-Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193540 (cherry picked from commit 64e193974ee448f78e0a5775a440094901590afb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idbdbeb9d229eff94a7a94af5dc4844a295458200 Reviewed-on: http://review.coreboot.org/7262 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-04-08 03:59:53 +02:00
hex "256K bytes left for TZBSP"
ipq8064: Configure proper bootblock stack and load address The SBL3 currently seems to be preventing the bootblock from being loaded into the IMEM. As a temporary measure, map bootblock into DRAM (as it is available after SBL2 finished running) and specify the correct stack space. BUG=chrome-os-partner:27784 TEST=not much testing yet, just verify 'emerge-storm coreboot' still succeeds. Original-Change-Id: Ibe9d4911ad22ada1bbd01af54a2ef80009df3a28 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196168 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 950323d6091c3b795034c24a08b6c176f56f0e0f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib3ec21f2cb4058b3e3cc82864de89dadf3b6aa84 Reviewed-on: http://review.coreboot.org/7268 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-22 03:53:47 +02:00
default 0x40600000
config STACK_TOP
soc/qualcomm/ipq806x/Kconfig: Fix indent style Change-Id: I72c9c1f5811fafaeec9572b05726d5677e2c28b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7669 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06 08:34:40 +01:00
hex
default 0x40600000
ipq8064: Configure proper bootblock stack and load address The SBL3 currently seems to be preventing the bootblock from being loaded into the IMEM. As a temporary measure, map bootblock into DRAM (as it is available after SBL2 finished running) and specify the correct stack space. BUG=chrome-os-partner:27784 TEST=not much testing yet, just verify 'emerge-storm coreboot' still succeeds. Original-Change-Id: Ibe9d4911ad22ada1bbd01af54a2ef80009df3a28 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196168 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 950323d6091c3b795034c24a08b6c176f56f0e0f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib3ec21f2cb4058b3e3cc82864de89dadf3b6aa84 Reviewed-on: http://review.coreboot.org/7268 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-22 03:53:47 +02:00
config STACK_BOTTOM
soc/qualcomm/ipq806x/Kconfig: Fix indent style Change-Id: I72c9c1f5811fafaeec9572b05726d5677e2c28b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7669 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06 08:34:40 +01:00
hex
default 0x405fc000
Provide ability to integrate with QComm SBLs Ipq8064 SBLs initialize the hardware to prepare it to run an arbitrary user provided bootloader. The only bootloader requirements imposed by the SBLs are that it is concatenated with the SBL chunks in the bootprm AND it uses MBN encapsulation (mostly to specify the size and load address). This patch adds configuration options to specify the location of the SBL blobs and to require MBN encapsulation of the bootblock. BRANCH=none BUG=chrome-os-partner:27784 TEST=manual - the below demonstrates added encapsulation, no code run attempts have been made yet: $ FEATURES=noclean emerge-storm coreboot $ cd /build/storm/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999 $ \od -t x4 build/cbfs/fallback/bootblock.bin | head -3 0000000 00000005 00000003 00000000 2a010000 0000020 00000be0 00000be0 2a010be0 00000000 0000040 2a010be0 00000000 e32bf0df e59f0030 Original-Change-Id: Iae30ad08059e2b35c434ac25a410ac2017752957 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193511 (cherry picked from commit bf16ea915c723ab124d817e3b0d950282e3cf1c1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53c71d382ec1d826f530d7afb545f64ec4eaf96b Reviewed-on: http://review.coreboot.org/7261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-04-08 00:26:39 +02:00
soc/qualcomm: Add generic support skeleton for ipq806x Skeleton for soc ipq806x Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911) soc/ipq806x: Disable LPAE mode. LPAE (large physical address extension) is not available on this SOC core, do not enable it. Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani <deepad@quicinc.com> (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b) Squashed 2 commits for the Qualcomm ipq806x SOC. Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6963 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2014-03-19 22:29:48 +01:00
endif
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