117 lines
3 KiB
C
117 lines
3 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef NORTHBRIDGE_INTEL_PINEVIEW_H
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#define NORTHBRIDGE_INTEL_PINEVIEW_H
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#include <northbridge/intel/pineview/iomap.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define EPBAR 0x40
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#define MCHBAR 0x48
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#define PCIEXBAR 0x60
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#define DMIBAR 0x68
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#define PMIOBAR 0x78
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#define GGC 0x52 /* GMCH Graphics Control */
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_D0F0 (1 << 0)
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#define DEVEN_D1F0 (1 << 1)
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#define DEVEN_D2F0 (1 << 3)
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#define DEVEN_D2F1 (1 << 4)
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#ifndef BOARD_DEVEN
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#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
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#endif /* BOARD_DEVEN */
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#define PAM0 0x90
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#define PAM1 0x91
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#define PAM2 0x92
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#define PAM3 0x93
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#define PAM4 0x94
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#define PAM5 0x95
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#define PAM6 0x96
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#define LAC 0x97 /* Legacy Access Control */
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#define REMAPBASE 0x98
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#define REMAPLIMIT 0x9a
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#define SMRAM 0x9d /* System Management RAM Control */
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#define ESMRAM 0x9e /* Extended System Management RAM Control */
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#define TOM 0xa0
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#define TOUUD 0xa2
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#define GBSM 0xa4
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#define BGSM 0xa8
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#define TSEGMB 0xac
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#define TOLUD 0xb0 /* Top of Low Used Memory */
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#define ERRSTS 0xc8
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#define ERRCMD 0xca
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#define SMICMD 0xcc
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#define SCICMD 0xce
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#define CGDIS 0xd8
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#define SKPAD 0xdc /* Scratchpad Data */
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#define CAPID0 0xe0
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#define DEV0T 0xf0
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#define MSLCK 0xf4
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#define MID0 0xf8
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#define DEBUP0 0xfc
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/* Device 0:1.0 PCI configuration space (PCI Express) */
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#define BCTRL1 0x3e /* 16bit */
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#define PEGSTS 0x214 /* 32bit */
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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#define GMADR 0x18
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#define GTTADR 0x1c
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#define BSM 0x5c
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#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */
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/*
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* MCHBAR
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*/
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#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
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#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
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#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
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/*
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* EPBAR - Egress Port Root Complex Register Block
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*/
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#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
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#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
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#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
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/*
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* DMIBAR
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*/
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#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
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#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
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#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
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/* provided by mainboard code */
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void setup_ich7_gpios(void);
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#endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */
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