88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <device/mmio.h>
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#include <delay.h>
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#include <soc/dsi.h>
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#include <soc/pll.h>
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void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
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{
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unsigned int txdiv, txdiv0, txdiv1;
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u64 pcw;
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if (data_rate >= 2000) {
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txdiv = 1;
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txdiv0 = 0;
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txdiv1 = 0;
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} else if (data_rate >= 1000) {
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txdiv = 2;
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txdiv0 = 1;
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txdiv1 = 0;
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} else if (data_rate >= 500) {
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txdiv = 4;
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txdiv0 = 2;
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txdiv1 = 0;
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} else if (data_rate > 250) {
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/* Be aware that 250 is a special case that must use txdiv=4. */
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txdiv = 8;
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txdiv0 = 3;
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txdiv1 = 0;
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} else {
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/* MIN = 125 */
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assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ);
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txdiv = 16;
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txdiv0 = 4;
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txdiv1 = 0;
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}
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clrbits_le32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
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setbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
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udelay(30);
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clrbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
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pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1);
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pcw <<= 24;
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pcw /= CLK26M_HZ / MHz;
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write32(&mipi_tx->pll_con0, pcw);
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clrsetbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
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udelay(30);
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setbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
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/* BG_LPF_EN / BG_CORE_EN */
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write32(&mipi_tx->lane_con, 0x3fff0180);
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udelay(40);
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write32(&mipi_tx->lane_con, 0x3fff00c0);
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/* Switch OFF each Lane */
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clrbits_le32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits_le32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits_le32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits_le32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits_le32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
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setbits_le32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
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}
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void mtk_dsi_reset(void)
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{
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write32(&dsi0->dsi_force_commit,
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DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS);
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write32(&dsi0->dsi_con_ctrl, 1);
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write32(&dsi0->dsi_con_ctrl, 0);
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}
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