48 lines
1.4 KiB
Markdown
48 lines
1.4 KiB
Markdown
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# RISCV architecture documentation
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This section contains documentation about coreboot on RISCV architecture.
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## Mode usage
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All stages run in M mode.
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Payloads have a choice of managing M mode activity: they can control
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everything or nothing.
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Payloads run from the romstage (i.e. rampayloads) are started in M mode.
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The payload must, for example, prepare and install its own SBI.
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Payloads run from the ramstage are started in S mode, and trap delegation
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will have been done. These payloads rely on the SBI and can not replace it.
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## Stage handoff protocol
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On entry to a stage or payload,
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* all harts are running.
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* A0 is the hart ID
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* A1 is the pointer to the Flattened Device Tree (FDT).
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## Additional payload handoff requirements
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The location of cbmem should be placed in a node in the FDT.
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## Trap delegation
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Traps are delegated in the ramstage.
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## SMP within a stage
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At the beginning of each stage, all harts save 0 are spinning in a loop on a semaphore.
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At the end of the stage harts 1..max are released by changing the
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semaphore.
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A possible way to do this is to have a pointer to a struct containing variables, e.g.
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```c
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struct blocker {
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void (*fn)(); // never returns
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}
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```
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The hart blocks until fn is non-null, and then calls it.
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If fn returns we will panic if possible, but behavior
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is largely undefined.
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Only hart 0 runs through most of the code in each stage.
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