2011-01-20 05:45:48 +01:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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2013-02-23 18:37:27 +01:00
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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2011-01-20 05:45:48 +01:00
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*/
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2013-06-25 22:17:43 +02:00
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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2011-01-20 05:45:48 +01:00
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#include <arch/io.h>
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2013-03-21 19:51:41 +01:00
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#include <reset.h>
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2011-01-20 05:45:48 +01:00
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2013-03-21 19:51:41 +01:00
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#include <northbridge/amd/amdk8/reset_test.c>
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2011-01-20 05:45:48 +01:00
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void hard_reset(void)
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{
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set_bios_reset();
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/* Try rebooting through port 0xcf9 */
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/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
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outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
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outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
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}
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