2013-03-15 23:57:13 +01:00
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/*
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* Compile and dump the device tree
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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#include <stdio.h>
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/* you can't include string.h due to conflicts with coreboot prototypes. */
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void *memcpy(void *m1, void *m2, size_t s);
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struct device_operations default_dev_ops_root = {
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.read_resources = NULL,
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.set_resources = NULL,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = NULL,
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.reset_bus = NULL,
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};
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extern struct device dev_root;
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struct device *all_devices = &dev_root;
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const char mainboard_name[] = "showdt";
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/*
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* Warning: This function uses a static buffer. Don't call it more than once
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* from the same print statement!
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*/
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const char *dev_path(device_t dev)
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{
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static char buffer[DEVICE_PATH_MAX];
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buffer[0] = '\0';
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if (!dev) {
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memcpy(buffer, "<null>", 7);
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} else {
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switch(dev->path.type) {
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case DEVICE_PATH_ROOT:
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memcpy(buffer, "Root Device", 12);
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break;
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case DEVICE_PATH_PCI:
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#if CONFIG_PCI_BUS_SEGN_BITS
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sprintf(buffer, "PCI: %04x:%02x:%02x.%01x",
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dev->bus->secondary >> 8,
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dev->bus->secondary & 0xff,
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PCI_SLOT(dev->path.pci.devfn),
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PCI_FUNC(dev->path.pci.devfn));
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#else
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sprintf(buffer, "PCI: %02x:%02x.%01x",
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dev->bus->secondary,
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PCI_SLOT(dev->path.pci.devfn),
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PCI_FUNC(dev->path.pci.devfn));
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#endif
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break;
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case DEVICE_PATH_PNP:
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sprintf(buffer, "PNP: %04x.%01x",
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dev->path.pnp.port, dev->path.pnp.device);
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break;
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case DEVICE_PATH_I2C:
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sprintf(buffer, "I2C: %02x:%02x",
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dev->bus->secondary,
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dev->path.i2c.device);
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break;
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case DEVICE_PATH_APIC:
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sprintf(buffer, "APIC: %02x",
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dev->path.apic.apic_id);
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break;
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case DEVICE_PATH_IOAPIC:
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sprintf(buffer, "IOAPIC: %02x",
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dev->path.ioapic.ioapic_id);
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break;
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case DEVICE_PATH_DOMAIN:
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sprintf(buffer, "DOMAIN: %04x",
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dev->path.domain.domain);
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break;
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case DEVICE_PATH_CPU_CLUSTER:
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sprintf(buffer, "CPU_CLUSTER: %01x",
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dev->path.cpu_cluster.cluster);
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break;
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case DEVICE_PATH_CPU:
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sprintf(buffer, "CPU: %02x", dev->path.cpu.id);
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break;
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case DEVICE_PATH_CPU_BUS:
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sprintf(buffer, "CPU_BUS: %02x", dev->path.cpu_bus.id);
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break;
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default:
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printf("Unknown device path type: %d\n",
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dev->path.type);
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break;
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}
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}
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return buffer;
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}
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void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum)
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{
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char depth_str[20] = "";
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int i;
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struct device *sibling;
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struct bus *link;
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for (i = 0; i < depth; i++)
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depth_str[i] = ' ';
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depth_str[i] = '\0';
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printf("%s%s: enabled %d%s\n",
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depth_str, dev_path(dev), dev->enabled,
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dev->chip_ops ? ":has a chip":"");
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for (link = dev->link_list; link; link = link->next) {
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for (sibling = link->children; sibling;
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sibling = sibling->sibling)
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show_devs_tree(sibling, debug_level, depth + 1, i);
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}
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}
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void show_all_devs_tree(int debug_level, const char *msg)
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{
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printf("Show all devs in tree form...%s\n", msg);
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show_devs_tree(all_devices, debug_level, 0, -1);
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}
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void show_devs_subtree(struct device *root, int debug_level, const char *msg)
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{
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printf("Show all devs in subtree %s...%s\n",
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dev_path(root), msg);
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printf("%s\n", msg);
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show_devs_tree(root, debug_level, 0, -1);
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}
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void show_all_devs(int debug_level, const char *msg)
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{
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struct device *dev;
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printf("Show all devs...%s\n", msg);
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for (dev = all_devices; dev; dev = dev->next) {
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printf("%s: enabled %d%s\n",
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dev_path(dev), dev->enabled,
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dev->chip_ops ? ":has a chip":"");
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}
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}
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main()
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{
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show_all_devs(1, "");
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show_all_devs_tree(1, "");
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}
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/*
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* Example: (yank this and paste into M-x compile in emacs)
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* or tail -2 showdt.c | head -1 |sh
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* or whatever.
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ARM: Generalize armv7 as arm.
There are ARM systems which are essentially heterogeneous multicores where
some cores implement a different ARM architecture version than other cores. A
specific example is the tegra124 which boots on an ARMv4 coprocessor while
most code, including most of the firmware, runs on the main ARMv7 core. To
support SOCs like this, the plan is to generalize the ARM architecture so that
all versions are available, and an SOC/CPU can then select what architecture
variant should be used for each component of the firmware; bootblock,
romstage, and ramstage.
Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171338
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
ARM: Split out ARMv7 code and make it possible to have other arch versions.
We don't always want to use ARMv7 code when building for ARM, so we should
separate out the ARMv7 code so it can be excluded, and also make it possible
to include code for some other version of the architecture instead, all per
build component for cases where we need more than one architecture version
at a time.
The tegra124 bootblock will ultimately need to be ARMv4, but until we have
some ARMv4 code to switch over to we can leave it set to ARMv7.
Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7
Reviewed-on: https://chromium-review.googlesource.com/171400
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483)
Squashed two related patches for splitting ARM support into general
ARM support and ARMv7 specific pieces.
Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6782
Tested-by: build bot (Jenkins)
2013-10-01 08:00:33 +02:00
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cc -I ../src -I ../src/include -I ../src/arch/arm/include/ -include build/mainboard/google/snow/static.c showdt.c
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2013-03-15 23:57:13 +01:00
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*/
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