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coreboot-kgpe-d16/src/mainboard/google/samus/acpi_tables.c

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samus: Add coreboot board Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-03 01:10:54 +02:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <ec/google/chromeec/ec.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include "thermal.h"
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
samus: Change thermal behavior to match other haswell platforms Change-Id: Ia835f16b156949f1841210c4a469223d5df28a54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174087 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8e51d1d74cdcadde9cbf10e8321d601b099c46bc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-12 05:50:05 +02:00
gnvs->tmps = TEMPERATURE_SENSOR_ID;
samus: Add coreboot board Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-03 01:10:54 +02:00
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
gnvs->tmax = MAX_TEMPERATURE;
samus: Change thermal behavior to match other haswell platforms Change-Id: Ia835f16b156949f1841210c4a469223d5df28a54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174087 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8e51d1d74cdcadde9cbf10e8321d601b099c46bc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-12 05:50:05 +02:00
gnvs->f0pw = EC_THROTTLE_POWER_LIMIT;
samus: Add coreboot board Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-03 01:10:54 +02:00
gnvs->flvl = 1;
}
haswell: Move to per-device ACPI Change-Id: Ic724dcf516d9cb78e89698da603151a32d24e978 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6814 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-08-31 17:43:51 +02:00
void acpi_create_gnvs(global_nvs_t *gnvs)
samus: Add coreboot board Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-03 01:10:54 +02:00
{
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
gnvs->s3u1 = 1;
/* Disable USB ports in S5 */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
/* TPM Present */
gnvs->tpmp = 1;
/* IGD Displays */
gnvs->ndid = 3;
gnvs->did[0] = 0x80000100;
gnvs->did[1] = 0x80000240;
gnvs->did[2] = 0x80000410;
gnvs->did[3] = 0x80000410;
gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
acpi_update_thermal_table(gnvs);
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
/* INT_SRC_OVR */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
samus: Add ACPI MADT interrupt override for GPIO IRQ 14 This interrupt needs to be specified in the MADT before it can be used by the kernel driver. Change-Id: Ic920a792a203cb06cd4529815680584a21532106 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171902 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a330fddb62cb6346ad66ceb5b5c32b66aecd81e2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6778 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2013-10-04 20:54:54 +02:00
/* GPIO Controller */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 14, 14, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
samus: Add coreboot board Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-03 01:10:54 +02:00
return current;
}
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
return current;
}
unsigned long acpi_fill_srat(unsigned long current)
{
/* No NUMA, no SRAT */
return current;
}
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