2007-04-22 21:08:13 +02:00
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/*
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2008-01-18 11:35:56 +01:00
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* This file is part of the coreboot project.
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2007-04-22 21:08:13 +02:00
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*
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* Copyright (C) 2005 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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2005-07-08 04:49:49 +02:00
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pciexp.h>
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static void pciexp_tune_dev(device_t dev)
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{
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2010-10-18 02:00:57 +02:00
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unsigned int cap;
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2011-04-21 22:24:43 +02:00
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#if CONFIG_PCIE_TUNING
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2010-11-05 00:23:47 +01:00
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u32 reg32;
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#endif
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2005-07-08 04:49:49 +02:00
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cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
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2010-10-18 02:00:57 +02:00
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if (!cap)
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2005-07-08 04:49:49 +02:00
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return;
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2010-10-18 02:00:57 +02:00
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2011-04-21 22:24:43 +02:00
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#if CONFIG_PCIE_TUNING
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2010-03-22 12:42:32 +01:00
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printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
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2010-01-17 14:54:08 +01:00
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2010-11-05 00:23:47 +01:00
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// TODO make this depending on ASPM.
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/* Enable ASPM role based error reporting. */
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2010-01-17 14:54:08 +01:00
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reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
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reg32 |= PCI_EXP_DEVCAP_RBER;
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pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
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#endif
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2005-07-08 04:49:49 +02:00
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}
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2010-10-18 02:00:57 +02:00
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unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
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unsigned int max_devfn, unsigned int max)
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2005-07-08 04:49:49 +02:00
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{
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device_t child;
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2010-10-18 02:00:57 +02:00
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2005-07-08 04:49:49 +02:00
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max = pci_scan_bus(bus, min_devfn, max_devfn, max);
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2010-10-18 02:00:57 +02:00
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for (child = bus->children; child; child = child->sibling) {
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if ((child->path.pci.devfn < min_devfn) ||
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(child->path.pci.devfn > max_devfn)) {
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2005-07-08 04:49:49 +02:00
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continue;
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}
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pciexp_tune_dev(child);
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}
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return max;
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}
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unsigned int pciexp_scan_bridge(device_t dev, unsigned int max)
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{
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return do_pci_scan_bridge(dev, max, pciexp_scan_bus);
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}
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/** Default device operations for PCI Express bridges */
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static struct pci_operations pciexp_bus_ops_pci = {
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.set_subsystem = 0,
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};
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struct device_operations default_pciexp_ops_bus = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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2010-10-18 02:00:57 +02:00
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.init = 0,
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.scan_bus = pciexp_scan_bridge,
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2005-07-08 04:49:49 +02:00
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.enable = 0,
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.reset_bus = pci_bus_reset,
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.ops_pci = &pciexp_bus_ops_pci,
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};
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