2019-11-01 13:56:56 +01:00
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/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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2020-03-23 05:43:10 +01:00
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#include <soc/gpe.h>
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/* XHCI Controller 0:14.0 */
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Device (XHCI)
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{
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Name (_ADR, 0x00140000)
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Name (_PRW, Package () { GPE0_PME_B0, 3 })
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Name (_S3D, 3) /* D3 supported in S3 */
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Name (_S0W, 3) /* D3 can wake device in S0 */
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Name (_S3W, 3) /* D3 can wake system from S3 */
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Method (_PS0, 0, Serialized)
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{
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}
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Method (_PS3, 0, Serialized)
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{
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}
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/* Root Hub for Tigerlake-LP PCH */
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Device (RHUB)
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{
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Name (_ADR, Zero)
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/* USB2 */
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Device (HS01) { Name (_ADR, 1) }
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Device (HS02) { Name (_ADR, 2) }
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Device (HS03) { Name (_ADR, 3) }
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Device (HS04) { Name (_ADR, 4) }
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Device (HS05) { Name (_ADR, 5) }
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Device (HS06) { Name (_ADR, 6) }
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Device (HS07) { Name (_ADR, 7) }
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Device (HS08) { Name (_ADR, 8) }
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Device (HS09) { Name (_ADR, 9) }
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Device (HS10) { Name (_ADR, 10) }
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/* USB3 */
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Device (SS01) { Name (_ADR, 13) }
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Device (SS02) { Name (_ADR, 14) }
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Device (SS03) { Name (_ADR, 15) }
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Device (SS04) { Name (_ADR, 16) }
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}
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}
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