2013-05-16 14:45:57 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Power setup code for EXYNOS5 */
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#include <arch/io.h>
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#include <arch/hlt.h>
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2013-08-29 23:17:36 +02:00
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#include <console/console.h>
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2013-06-03 22:03:50 +02:00
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#include "dmc.h"
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2013-05-16 14:45:57 +02:00
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#include "power.h"
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2013-05-17 20:17:15 +02:00
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#include "setup.h"
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2013-05-16 14:45:57 +02:00
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2013-05-17 20:17:15 +02:00
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void ps_hold_setup(void)
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2013-05-16 14:45:57 +02:00
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{
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/* Set PS-Hold high */
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2013-08-29 23:17:36 +02:00
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setbits_le32(&exynos_power->ps_hold_ctrl,
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POWER_PS_HOLD_CONTROL_DATA_HIGH);
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2013-05-16 14:45:57 +02:00
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}
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void power_reset(void)
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{
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/* Clear inform1 so there's no change we think we've got a wake reset */
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2013-08-29 23:17:36 +02:00
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exynos_power->inform1 = 0;
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2013-05-16 14:45:57 +02:00
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2013-08-29 23:17:36 +02:00
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setbits_le32(&exynos_power->sw_reset, 1);
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2013-05-16 14:45:57 +02:00
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}
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/* This function never returns */
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void power_shutdown(void)
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{
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2013-08-29 23:17:36 +02:00
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clrbits_le32(&exynos_power->ps_hold_ctrl,
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POWER_PS_HOLD_CONTROL_DATA_HIGH);
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2013-05-16 14:45:57 +02:00
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hlt();
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}
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void power_enable_dp_phy(void)
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{
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2013-08-29 23:17:36 +02:00
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setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
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2013-05-16 14:45:57 +02:00
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}
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void power_enable_hw_thermal_trip(void)
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{
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/* Enable HW thermal trip */
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2013-08-29 23:17:36 +02:00
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setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
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2013-05-16 14:45:57 +02:00
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}
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uint32_t power_read_reset_status(void)
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{
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2013-08-29 23:17:36 +02:00
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return exynos_power->inform1;
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2013-05-16 14:45:57 +02:00
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}
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void power_exit_wakeup(void)
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{
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typedef void (*resume_func)(void);
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2013-08-29 23:17:36 +02:00
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((resume_func)exynos_power->inform0)();
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2013-05-16 14:45:57 +02:00
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}
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int power_init(void)
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{
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ps_hold_setup();
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return 0;
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}
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void power_enable_xclkout(void)
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{
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/* use xxti for xclk out */
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2013-08-29 23:17:36 +02:00
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clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
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PMU_DEBUG_XXTI);
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2013-05-16 14:45:57 +02:00
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}
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2013-09-24 09:51:05 +02:00
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void power_release_uart_retention(void)
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{
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writel(1 << 28, &exynos_power->padret_uart_opt);
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}
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