53 lines
1.6 KiB
C
53 lines
1.6 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <usbdebug.h>
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#include <device/pci_def.h>
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#include "sb800.h"
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#ifndef SB800_DEVN_BASE
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#define SB800_DEVN_BASE 0
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#endif
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#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20)
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#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80)
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void set_debug_port(unsigned int port)
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{
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u32 reg32;
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/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
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reg32 = read32(DEBUGPORT_MISC_CONTROL);
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reg32 &= ~(0xf << 28);
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reg32 |= (port << 28);
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reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
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write32(DEBUGPORT_MISC_CONTROL, reg32);
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}
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void sb800_enable_usbdebug(unsigned int port)
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{
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pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5),
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EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
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pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enabe */
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set_debug_port(port);
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}
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