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coreboot-kgpe-d16/spd/ddr4/memory_parts.json

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spd: Generate SPDs under spd/ using unified spd_gen tool Use the new unified version of the spd_gen tool to generate all LP4x and DDR4 SPDs, storing them in a new spd/ directory. Storing them in a common location allows platforms with the same SPD requirements to share SPD files, reducing duplication compared to storing SPDs in soc/ and mainboard/ directories. For each memory technology there are multiple sets of SPDs. Each set corresponds to a set of platforms with different SPD requirements, e.g. due to different memory training code expectations. A manifest file (platforms_manifest.generated.txt) lists the platform -> set mappings. Commands used to generate SPDs: cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \ spd/lp4x/memory_parts.json cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09 05:08:19 +02:00
// Global list of ddr4 memory part attributes.
// These attributes match the part specifications and are independent
// of any SoC expectations.
{
"parts": [
{
"name": "H5AN8G6NDJR-XNC",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
"name": "MT40A512M16TB-062E:J",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
"name": "H5ANAG6NCMR-XNC",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 2,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. 1.1 / Sep.2017
"name": "HMA851S6CJR6N-VK",
"attribs": {
"speedMTps": 2666,
"CL_nRCD_nRP": 19,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. 1.5, Apr. 2017
"name": "K4A8G165WC-BCTD",
"attribs": {
"speedMTps": 2666,
"CL_nRCD_nRP": 19,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. 1.3 / Jun.2018
"name": "H5AN8G6NCJR-VKC",
"attribs": {
"speedMTps": 2666,
"CL_nRCD_nRP": 19,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. F 10/17 EN
"name": "MT40A1G16KNR-075:E",
"attribs": {
"speedMTps": 2666,
"CL_nRCD_nRP": 18,
"capacityPerDieGb": 8,
"diesPerPackage": 2,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. 1.4, Jul. 2017
"name": "K4AAG165WB-MCTD",
"attribs": {
"speedMTps": 2666,
"CL_nRCD_nRP": 19,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 8,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. 1.0 / Aug.2018
"name": "H5ANAG6NCMR-VKC",
"attribs": {
"speedMTps": 2666,
"CL_nRCD_nRP": 19,
"capacityPerDieGb": 8,
"diesPerPackage": 2,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. 0.5, Jun. 2019
"name": "K4A8G165WC-BCWE",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. G 08/2020 EN
"name": "MT40A1G16KD-062E:E",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 16,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1,
// Table 158 - Refersh Timing - 16Gb
"TRFC1MinPs": 350000,
"TRFC2MinPs": 260000,
"TRFC4MinPs": 160000
}
},
{
// Datasheet Revision: Rev. 0.5, Feb. 2019
"name": "K4AAG165WA-BCWE",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 16,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1,
// Table 57 - 16Gb
"TRFC1MinPs": 350000,
"TRFC2MinPs": 260000,
"TRFC4MinPs": 160000
}
},
{
// Datasheet Revision: Rev. 1.5 / Mar.2019
"name": "H5AN8G6NCJR-XNC",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. 1.0, Dec. 2019
"name": "K4AAG165WA-BCTD",
"attribs": {
"speedMTps": 2666,
"CL_nRCD_nRP": 19,
"capacityPerDieGb": 16,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1,
// Table 41 - Note: Both 550ns and 350ns tRFC1 is supported
"TRFC1MinPs": 350000,
"TRFC2MinPs": 260000,
"TRFC4MinPs": 160000
}
},
{
// Datasheet Revision: Rev. 1.0, Feb. 2020
"name": "H5ANAG6NDMR-XNC",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 2,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. 1.4, May. 2020
"name": "H5ANAG6NCJR-XNC",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 16,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
mb/google/volteer/eldrid: Add new DDR4 part H5AG36EXNDX019 Hynix H5AG36EXNDX019 is used by the volteer variant Eldrid. Add it to the DDR4 parts list and regenerate the SPDs using spd_gen. BUG=b:236739240 BRANCH=Volteer TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I3383dfa4e87571d920144d204270cdf646a19abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-13 09:50:25 +02:00
{
// Datasheet Revision: Rev. 1.0 Dec. 2021
spd/ddr4: Correct Hynix ddr4 part number from H5AG36EXNDX019 to H5AG36EXNDX017 Correct Hynix ddr4 part number H5AG36EXNDX019 to H5AG36EXNDX017 by Hynix Memory spec. BUG=b:236739240 BRANCH=Volteer TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I6195fa1402691afc303f5223de48f552660cd97f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71159 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20 09:41:34 +01:00
"name": "H5AG36EXNDX017",
mb/google/volteer/eldrid: Add new DDR4 part H5AG36EXNDX019 Hynix H5AG36EXNDX019 is used by the volteer variant Eldrid. Add it to the DDR4 parts list and regenerate the SPDs using spd_gen. BUG=b:236739240 BRANCH=Volteer TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I3383dfa4e87571d920144d204270cdf646a19abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-13 09:50:25 +02:00
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
spd: Generate SPDs under spd/ using unified spd_gen tool Use the new unified version of the spd_gen tool to generate all LP4x and DDR4 SPDs, storing them in a new spd/ directory. Storing them in a common location allows platforms with the same SPD requirements to share SPD files, reducing duplication compared to storing SPDs in soc/ and mainboard/ directories. For each memory technology there are multiple sets of SPDs. Each set corresponds to a set of platforms with different SPD requirements, e.g. due to different memory training code expectations. A manifest file (platforms_manifest.generated.txt) lists the platform -> set mappings. Commands used to generate SPDs: cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \ spd/lp4x/memory_parts.json cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09 05:08:19 +02:00
{
// Datasheet Revision: Rev. 0.0, Apr. 2020
"name": "K4AAG165WB-BCWE",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 16,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
// Datasheet Revision: Rev. A 03/2021 EN
"name": "MT40A1G16RC-062E:B",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 16,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
"name": "MT40A512M16TB-062E:R",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
spd: Add SPD for 4JQA-0622AD to spd/ Since generating the SPDs under spd/, a new part was added in https://review.coreboot.org/57550. Regenerate the SPDs to include this new part. Commands used: cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie673d1a386479f690182050ce4fee7d252ec9530 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-22 01:27:48 +02:00
},
{
"name": "4JQA-0622AD",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
spd: Generate SPDs under spd/ using unified spd_gen tool Use the new unified version of the spd_gen tool to generate all LP4x and DDR4 SPDs, storing them in a new spd/ directory. Storing them in a common location allows platforms with the same SPD requirements to share SPD files, reducing duplication compared to storing SPDs in soc/ and mainboard/ directories. For each memory technology there are multiple sets of SPDs. Each set corresponds to a set of platforms with different SPD requirements, e.g. due to different memory training code expectations. A manifest file (platforms_manifest.generated.txt) lists the platform -> set mappings. Commands used to generate SPDs: cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \ spd/lp4x/memory_parts.json cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09 05:08:19 +02:00
}
]
}