coreboot-kgpe-d16/payloads/libpayload/configs/defconfig-mips

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#
# Automatically generated make config: don't edit
# libpayload version: 0.2.0
# Sat Mar 21 10:22:59 2015
#
#
# Generic Options
#
# CONFIG_LP_GPL is not set
# CONFIG_LP_EXPERIMENTAL is not set
# CONFIG_LP_OBSOLETE is not set
# CONFIG_LP_DEVELOPER is not set
# CONFIG_LP_CHROMEOS is not set
#
# Architecture Options
#
# CONFIG_LP_ARCH_ARM is not set
# CONFIG_LP_ARCH_X86 is not set
# CONFIG_LP_ARCH_ARM64 is not set
CONFIG_LP_ARCH_MIPS=y
# CONFIG_LP_MEMMAP_RAM_ONLY is not set
#
# Standard Libraries
#
CONFIG_LP_LIBC=y
CONFIG_LP_CURSES=y
# CONFIG_LP_TINYCURSES is not set
CONFIG_LP_PDCURSES=y
CONFIG_LP_CBFS=y
CONFIG_LP_LZMA=y
#
# Console Options
#
# CONFIG_LP_SKIP_CONSOLE_INIT is not set
CONFIG_LP_CBMEM_CONSOLE=y
CONFIG_LP_SERIAL_CONSOLE=y
CONFIG_LP_8250_SERIAL_CONSOLE=y
# CONFIG_LP_S5P_SERIAL_CONSOLE is not set
serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32 We have two drivers for a 100%-identical peripheral right now, mostly because we couldn't come up with a good common name for it back when we checked it in. That seems like a pretty silly reason in the long run. Both Tegra and Rockchip SoCs contain UARTs that use the common 8250 register interface (at least for the very basic byte-per-byte transmit and receive parts we care about), memory-mapped with a 32-bit register stride. This patch combines them to a single 8250_mmio32 driver (which also fixes a problem when booting Rockchip without serial enabled, since that driver forgot to check for serial initialization when registering its console drivers). The register accesses are done using readl/writel (as Rockchip did before), since the registers are documented as 32-bit length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce APB accesses to have the full word length. Also fixed checkpatch stuff. A day may come when we can also merge this driver into the (completely different, with more complicated features and #ifdefs) 8250 driver for x86 (which has MMIO support for 8-bit register stride only), both here and in coreboot. But it is not this day. This day I just want to get rid of a 99% identical file without expending too much effort. BUG=None TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial enabled, both worked fine (although Veyron has another kernel issue). Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8 Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225102 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-22 23:12:50 +02:00
# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set
# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set
# CONFIG_LP_PL011_SERIAL_CONSOLE is not set
# CONFIG_LP_SERIAL_SET_SPEED is not set
# CONFIG_LP_SERIAL_ACS_FALLBACK is not set
CONFIG_LP_VIDEO_CONSOLE=y
CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y
CONFIG_LP_PC_KEYBOARD=y
CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y
# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set
#
# Drivers
#
# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set
CONFIG_LP_STORAGE=y
# CONFIG_LP_STORAGE_64BIT_LBA is not set
CONFIG_LP_STORAGE_ATA=y
CONFIG_LP_STORAGE_ATAPI=y
# CONFIG_LP_TIMER_NONE is not set
# CONFIG_LP_TIMER_MCT is not set
# CONFIG_LP_TIMER_TEGRA_1US is not set
# CONFIG_LP_TIMER_IPQ806X is not set
# CONFIG_LP_TIMER_RK is not set
# CONFIG_LP_TIMER_BG4CD is not set
CONFIG_LP_TIMER_IMG_PISTACHIO=y
# CONFIG_LP_USB is not set
# CONFIG_LP_USB_GEN_HUB is not set
# CONFIG_LP_BIG_ENDIAN is not set
CONFIG_LP_LITTLE_ENDIAN=y
# CONFIG_LP_IO_ADDRESS_SPACE is not set
CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y