114 lines
3 KiB
C
114 lines
3 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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/* This code is based on src/southbridge/intel/esb6300/esb6300_smbus.h */
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#include <device/smbus_def.h>
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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#define SMBSLVCMD 0x11
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#define SMBUS_TIMEOUT (100*1000*10)
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static void smbus_delay(void)
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{
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outb(0x80, 0x80);
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}
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static int smbus_wait_until_ready(u32 smbus_io_base)
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{
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u32 loops = SMBUS_TIMEOUT;
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u8 byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_io_base + SMBHSTSTAT);
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} while (byte & 1);
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return loops ? 0 : -1;
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}
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static int smbus_wait_until_done(u32 smbus_io_base)
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{
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u32 loops = SMBUS_TIMEOUT;
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u8 byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_io_base + SMBHSTSTAT);
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} while ((byte & 1) || (byte & ~((1 << 6)|(1 << 0))) == 0);
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return loops ? 0 : -1;
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}
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static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address)
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{
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u8 global_status_register;
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u8 byte;
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if (smbus_wait_until_ready(smbus_io_base) < 0) {
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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/* setup transaction */
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/* disable interrupts */
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outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
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/* set the command/address... */
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outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
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/* set up for a byte data read */
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outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
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/* clear the data byte...*/
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outb(0, smbus_io_base + SMBHSTDAT0);
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/* start the command */
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outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inb(smbus_io_base + SMBHSTSTAT);
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/* Ignore the In Use Status... */
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global_status_register &= ~(3 << 5);
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/* read results of transaction */
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byte = inb(smbus_io_base + SMBHSTDAT0);
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if (global_status_register != (1 << 1)) {
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return SMBUS_ERROR;
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}
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return byte;
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}
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