2020-06-29 21:54:20 +02:00
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# Purism Librem Mini
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2020-08-18 23:57:16 +02:00
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This page describes how to run coreboot on the [Purism Librem Mini].
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2020-06-29 21:54:20 +02:00
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```eval_rst
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+------------------+--------------------------------------------------+
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2020-08-18 23:57:16 +02:00
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| CPU | Intel Core i7-8565U |
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+------------------+--------------------------------------------------+
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| PCH | Whiskey Lake / Cannon Point LP |
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+------------------+--------------------------------------------------+
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| Super I/O, EC | ITE IT8528E |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine (CSME 12.x) |
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+------------------+--------------------------------------------------+
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```
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![](librem_mini.jpg)
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![](librem_mini_flash.jpg)
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## Required proprietary blobs
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To build a minimal working coreboot image some blobs are required (assuming
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only the BIOS region is being modified).
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```eval_rst
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+-----------------+---------------------------------+---------------------+
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| Binary file | Apply | Required / Optional |
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+=================+=================================+=====================+
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| FSP-M, FSP-S | Intel Firmware Support Package | Required |
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+-----------------+---------------------------------+---------------------+
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| microcode | CPU microcode | Required |
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+-----------------+---------------------------------+---------------------+
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| vgabios | VGA Option ROM | Optional |
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+-----------------+---------------------------------+---------------------+
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```
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FSP-M and FSP-S are obtained after splitting the Coffee Lake FSP binary (done
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automatically by the coreboot build system and included into the image) from
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the `3rdparty/fsp` submodule.
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Microcode updates are automatically included into the coreboot image by the build
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system from the `3rdparty/intel-microcode` submodule. Official Purism release
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images may include newer microcode, which is instead pulled from Purism's
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[purism-blobs] repository.
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VGA Option ROM is not required to boot, but if one needs graphics in pre-OS
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stage, it should be included (if not using FSP/GOP display init). It can
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be extracted via cbfstool from the existing board firmware or pulled from
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the [purism-blobs] repository.
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## Intel Management Engine
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The Librem Mini uses version 12.x of the Intel Management Engine (ME) /
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Converged Security Engine (CSE). The ME/CSE is disabled using the High
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Assurance Platform (HAP) bit, which puts the ME into a disabled state
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after platform bring-up (BUP) and disables all PCI/HECI interfaces.
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This can be verified via the coreboot cbmem utility:
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`sudo ./cbmem -1 | grep 'ME:'`
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provided coreboot has been modified to output the ME status even when
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the PCI device is not visible/active (as it is in Purism's release builds).
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## Flashing coreboot
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### Internal programming
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The main SPI flash can be accessed using [flashrom]. The first version
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supporting the chipset is flashrom v1.2. Firmware an be easily flashed
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with internal programmer (either BIOS region or full image).
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### External programming
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The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip,
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and has a diode attached to the VCC line for in-system programming.
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This chip is located on the bottom side of the board under the CPU heatsink,
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in line with the front USB 2.0 ports.
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One has to remove all screws (in order):
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* 2 top cover screws
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* 4 screws securing the mainboard to the chassis
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* 4 screws securing the heatsink/fan assembly to the mainboard (under the SODIMMs)
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The m.2 SSD will need to be removed if the Wi-Fi antenna are connected to
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an internal Wi-Fi/BT module. Use a SOIC-8 chip clip to program the chip.
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Specifically, it's a Winbond W25Q128JV (3.3V) - [datasheet][W25Q128JV].
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The EC firmware is stored on a separate SOIC-8 chip (a Winbond W25Q80DV),
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but is not protected by a diode and therefore cannot be read/written to without
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desoldering it from the mainboard.
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## Known issues
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* SeaBIOS can be finicky with detecting USB devices
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* Booting can sometimes hang when a bootsplash image is used with SeaBIOS
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and VGA option ROM display init, related to display mode changing
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* Issues with some SATA devices have been mitigated by limiting the SATA speed to 3Gbps
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until the correct HSIO PHY settings can be determined.
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## Working
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* External displays via HDMI/DislpayPort with VGA option ROM or FSP/GOP init
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(no libgfxinit support yet)
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* SeaBIOS (1.13.x), Tianocore (CorebootPayloadpkg), Heads (Purism downstream) payloads
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* Ethernet, m.2 2230 Wi-Fi
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* System firmware updates via flashrom
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* PCIe NVMe
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* m.2 and SATA III
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* Audio via front 3.5mm jack, HDMI, and DisplayPort
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* SMBus (reading SPD from DIMMs)
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* Initialization with CFL FSP 2.0
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* S3 Suspend/Resume
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* Booting PureOS 9.x, Debian 10.x, Qubes 4.0.3, Linux Mint 19.3, Windows 10 2004
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## Not working / untested
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* ITE IT8528E Super IO functions
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[Purism Librem Mini]: https://puri.sm/products/librem-mini/
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2020-08-18 23:57:16 +02:00
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[purism-blobs]: https://source.puri.sm/coreboot/purism-blobs
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2020-06-29 21:54:20 +02:00
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[W25Q128JV]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
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[flashrom]: https://flashrom.org/Flashrom
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