111 lines
3.2 KiB
Text
111 lines
3.2 KiB
Text
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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chip cpu/intel/model_1067x # CPU
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device lapic 0xACAC off end
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end
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end
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device domain 0 on # PCI domain
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device pci 0.0 on end # Host Bridge
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device pci 2.0 on end # Integrated graphics controller
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device pci 2.1 on end # Integrated graphics controller 2
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device pci 3.0 off end # ME
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device pci 3.1 off end # ME
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chip southbridge/intel/i82801jx # Southbridge
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register "gpe0_en" = "0x40"
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# Set AHCI mode.
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register "sata_port_map" = "0x1f"
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register "sata_clock_request" = "0"
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register "sata_traffic_monitor" = "0"
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# Enable PCIe ports 0,2,3 as slots.
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register "pcie_slot_implemented" = "0xb"
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device pci 19.0 on end # GBE
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device pci 1a.0 on end # USB
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device pci 1a.1 on end # USB
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device pci 1a.2 on end # USB
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device pci 1a.7 on end # USB
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device pci 1b.0 on end # Audio
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device pci 1c.0 on end # PCIe 1
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device pci 1c.1 off end # PCIe 2
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device pci 1c.2 on end # PCIe 3
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device pci 1c.3 on end # PCIe 4
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device pci 1c.4 off end # PCIe 5
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device pci 1c.5 off end # PCIe 6
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device pci 1d.0 on end # USB
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device pci 1d.1 on end # USB
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device pci 1d.2 on end # USB
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device pci 1d.7 on end # USB
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # ISA bridge
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chip superio/winbond/w83627dhg # Super I/O
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device pnp 2e.0 on # Floppy
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# GLOBAL
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 5
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drq 0x74 = 4
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end
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device pnp 2e.2 on # COM 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off end # COM 2
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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irq 0x70 = 1
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io 0x62 = 0x64
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irq 0xf0 = 0x85
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end
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device pnp 2e.6 off end # SPI
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device pnp 2e.7 on # GPIO 6
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irq 0x30 = 0x06
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end
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device pnp 2e.8 off end # WDTO# PLED
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device pnp 2e.9 on # GPIO 2,3,4,5
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irq 0x30 = 0x0a
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end
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device pnp 2e.a on # ACPI
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irq 0xe4 = 0x30 # power dram during S3
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end
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device pnp 2e.b on # Hardware monitor
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io 0x60 = 0x290
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end
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device pnp 2e.c off end # PECI, SST
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end
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end
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device pci 1f.1 on end # PATA/IDE
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device pci 1f.2 on end # SATA
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device pci 1f.3 on end # SMbus
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device pci 1f.4 off end
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device pci 1f.5 on end # IDE
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device pci 1f.6 off end
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end
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end
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end
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