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coreboot-kgpe-d16/src/include/spd_cache.h

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lib/spd_cache: add spd_cache common code This patch adds some spd_cache functions. They are for implementing the spd_cache. It's for reducing the SPD fetch time when device uses SODIMMs. The MRC cache also includes SPD data, but there is no public header file available to decode the struct of MRC. So SPD cache is another solution. BUG=b:146457985 BRANCH=None TEST=Build puff successfully and verified below two items. one DIMM save the boot time : 158ms two DIMM save the boot time : 265ms Change-Id: Ia48aa022fabf8949960a50597185c9d821399522 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-27 09:49:09 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SPD_CACHE_H
#define __SPD_CACHE_H
#include <spd_bin.h>
src/include: Add missing includes Change-Id: I746ea7805bae553a146130994d8174aa2e189610 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-12 09:03:22 +02:00
#include <stddef.h>
#include <stdint.h>
lib/spd_cache: add spd_cache common code This patch adds some spd_cache functions. They are for implementing the spd_cache. It's for reducing the SPD fetch time when device uses SODIMMs. The MRC cache also includes SPD data, but there is no public header file available to decode the struct of MRC. So SPD cache is another solution. BUG=b:146457985 BRANCH=None TEST=Build puff successfully and verified below two items. one DIMM save the boot time : 158ms two DIMM save the boot time : 265ms Change-Id: Ia48aa022fabf8949960a50597185c9d821399522 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-27 09:49:09 +02:00
src/lib: Add Kconfig option for SPD cache in FMAP Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30 21:30:15 +01:00
#define SPD_CACHE_FMAP_NAME (CONFIG_SPD_CACHE_FMAP_NAME)
lib/spd_cache: add spd_cache common code This patch adds some spd_cache functions. They are for implementing the spd_cache. It's for reducing the SPD fetch time when device uses SODIMMs. The MRC cache also includes SPD data, but there is no public header file available to decode the struct of MRC. So SPD cache is another solution. BUG=b:146457985 BRANCH=None TEST=Build puff successfully and verified below two items. one DIMM save the boot time : 158ms two DIMM save the boot time : 265ms Change-Id: Ia48aa022fabf8949960a50597185c9d821399522 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-27 09:49:09 +02:00
#define SC_SPD_NUMS (CONFIG_DIMM_MAX)
#define SC_SPD_OFFSET(n) (CONFIG_DIMM_SPD_SIZE * n)
#define SC_CRC_OFFSET (CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE)
#define SC_SPD_TOTAL_LEN (CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE)
#define SC_SPD_LEN (CONFIG_DIMM_SPD_SIZE)
#define SC_CRC_LEN (sizeof(uint16_t))
enum cb_err update_spd_cache(struct spd_block *blk);
enum cb_err load_spd_cache(uint8_t **spd_cache, size_t *spd_cache_sz);
bool spd_cache_is_valid(uint8_t *spd_cache, size_t spd_cache_sz);
bool check_if_dimm_changed(u8 *spd_cache, struct spd_block *blk);
enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk);
#endif