81 lines
2.9 KiB
Text
81 lines
2.9 KiB
Text
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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chip soc/nvidia/tegra124
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device cpu_cluster 0 on end
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# N.B. We ae not using the device tree in an effective way.
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# We need to change this in future such that the on-soc
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# devices are 'chips', which will allow us to go at them
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# in parallel. This is even easier on the ARM SOCs since there
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# are no single-access resources such as the infamous
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# cf8/cfc registers found on PCs.
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register "display_controller" = "TEGRA_ARM_DISPLAYA"
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register "xres" = "1366"
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register "yres" = "768"
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# this setting is what nvidia does; it makes no sense
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# and does not agree with hardware. Why'd they do it?
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register "framebuffer_bits_per_pixel" = "18"
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register "cache_policy" = "DCACHE_WRITETHROUGH"
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# With some help from the mainbaord designer
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register "backlight_en_gpio" = "GPIO(H2)"
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register "lvds_shutdown_gpio" = "0"
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register "backlight_vdd_gpio" = "GPIO(P2)"
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register "panel_vdd_gpio" = "0"
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register "pwm" = "GPIO(H1)"
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# taken from u-boot; these look wrong however.
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register "vdd_delay" = "400"
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register "vdd_data_delay" = "4"
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register "data_backlight_delay" = "203"
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register "backlight_pwm_delay" = "17"
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register "pwm_backlight_en_delay" = "15"
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# How to compute these: xrandr --verbose will give you this:
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#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
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# 2560 2608 2640 2720 hborder 0
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# 1700 1703 1713 1749 vborder 0
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#Then you can compute your values:
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#H front porch = 2608 - 2560 = 48
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#H sync = 2640 - 2608 = 32
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#H back porch = 2720 - 2640 = 80
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#V front porch = 1703 - 1700 = 3
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#V sync = 1713 - 1703 = 10
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#V back porch = 1749 - 1713 = 36
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#href_to_sync and vref_to_sync are from the vendor
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#this is just an example for a Pixel panel; other panels differ.
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# Here is a peppy panel:
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# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
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# h: width 1366 start 1502 end 1532 total 1592
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# v: height 768 start 776 end 788 total 800
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# These numbers were provided by Nvidia.
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register "href_to_sync" = "1"
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register "hfront_porch" = "44"
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register "hsync_width" = "46"
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register "hback_porch" = "44"
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register "vref_to_sync" = "1"
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register "vfront_porch" = "6"
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register "vsync_width" = "8"
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register "vback_porch" = "6"
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# we *know* the pixel clock for this system.
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register "pixel_clock" = "71"
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end
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