333 lines
9 KiB
C
333 lines
9 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 - 2009 coresystems GmbH
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2014 - 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <cpu/x86/smm.h>
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#include <string.h>
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#include <device/pci.h>
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#include <cpu/cpu.h>
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#include <cbmem.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/soc_util.h>
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#include <soc/pmc.h>
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#include <soc/systemagent.h>
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void acpi_init_gnvs(global_nvs_t *gnvs)
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{
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/* CPU core count */
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gnvs->pcnt = dev_count_cpu();
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/* Top of Low Memory (start of resource allocation) */
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gnvs->tolm = top_of_32bit_ram();
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#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
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/* Update the mem console pointer. */
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gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
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#endif
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/* MMIO Low/High & TSEG base and length */
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gnvs->mmiob = (u32)get_top_of_low_memory();
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gnvs->mmiol = (u32)(get_pciebase() - 1);
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gnvs->mmiohb = (u64)get_top_of_upper_memory();
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gnvs->mmiohl = (u64)(((u64)1 << CONFIG_CPU_ADDR_BITS) - 1);
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gnvs->tsegb = (u32)get_tseg_memory();
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gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory());
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}
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static int acpi_sci_irq(void)
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{
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int scis, sci_irq;
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device_t dev = get_pmc_dev();
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if (!dev)
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return 0;
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/* Determine how SCI is routed. */
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scis = pci_read_config32(dev, PMC_ACPI_CNT) & PMC_ACPI_CNT_SCIS_MASK;
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switch (scis) {
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case PMC_ACPI_CNT_SCIS_IRQ9:
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case PMC_ACPI_CNT_SCIS_IRQ10:
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case PMC_ACPI_CNT_SCIS_IRQ11:
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sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ9 + 9;
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break;
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case PMC_ACPI_CNT_SCIS_IRQ20:
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case PMC_ACPI_CNT_SCIS_IRQ21:
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case PMC_ACPI_CNT_SCIS_IRQ22:
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case PMC_ACPI_CNT_SCIS_IRQ23:
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sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ20 + 20;
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break;
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default:
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printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
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sci_irq = 9;
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break;
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}
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printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
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return sci_irq;
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}
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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u32 pciexbar_reg;
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int max_buses;
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pciexbar_reg = get_pciebase();
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max_buses = get_pcielength();
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if (!pciexbar_reg)
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return current;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
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pciexbar_reg, 0x0, 0x0,
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(u8)(max_buses - 1));
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return current;
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}
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void acpi_fill_in_fadt(acpi_fadt_t *fadt)
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{
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u16 pmbase = get_pmbase();
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/* System Management */
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fadt->sci_int = acpi_sci_irq();
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#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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#else
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fadt->smi_cmd = 0x00;
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fadt->acpi_enable = 0x00;
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fadt->acpi_disable = 0x00;
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#endif
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/* Power Control */
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fadt->s4bios_req = 0x0;
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fadt->pstate_cnt = 0;
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fadt->pm1a_evt_blk = pmbase + PM1_STS;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
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fadt->pm1b_cnt_blk = 0x0;
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fadt->pm2_cnt_blk = pmbase + PM2_CNT;
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fadt->pm_tmr_blk = pmbase + PM1_TMR;
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fadt->gpe0_blk = pmbase + GPE0_STS;
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fadt->gpe1_blk = 0;
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/* Control Registers - Length */
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 8;
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fadt->gpe1_blk_len = 0;
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fadt->gpe1_base = 0;
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fadt->cst_cnt = 0;
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
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fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
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fadt->duty_offset = 1;
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fadt->duty_width = 0;
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/* RTC Registers */
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fadt->day_alrm = 0x0D;
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fadt->mon_alrm = 0x00;
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fadt->century = 0x00;
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
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fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE |
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ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
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/* Reset Register */
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fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->reset_reg.addrl = 0xCF9;
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fadt->reset_reg.addrh = 0x00;
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fadt->reset_value = 6;
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/* PM1 Status & PM1 Enable */
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_evt_blk.bit_width = 32;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
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fadt->x_pm1a_evt_blk.addrh = 0x00;
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fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1b_evt_blk.bit_width = 0;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.access_size = 0;
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fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
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fadt->x_pm1b_evt_blk.addrh = 0x00;
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/* PM1 Control Registers */
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_cnt_blk.bit_width = 16;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
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fadt->x_pm1a_cnt_blk.addrh = 0x00;
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fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1b_cnt_blk.bit_width = 0;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.access_size = 0;
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fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
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fadt->x_pm1b_cnt_blk.addrh = 0x00;
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/* PM2 Control Registers */
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fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm2_cnt_blk.bit_width = 8;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
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fadt->x_pm2_cnt_blk.addrh = 0x00;
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/* PM1 Timer Register */
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
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fadt->x_pm_tmr_blk.addrh = 0x00;
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/* General-Purpose Event Registers */
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
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fadt->x_gpe0_blk.addrh = 0x00;
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fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe1_blk.bit_width = 0;
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fadt->x_gpe1_blk.bit_offset = 0;
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fadt->x_gpe1_blk.access_size = 0;
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fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
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fadt->x_gpe1_blk.addrh = 0x00;
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}
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void generate_cpu_entries(device_t device)
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{
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int core;
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int pcontrol_blk = get_pmbase(), plen = 6;
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int num_cpus = get_cpu_count();
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for (core = 0; core < num_cpus; core++) {
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if (core > 0) {
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pcontrol_blk = 0;
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plen = 0;
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}
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/* Generate processor \_PR.CPUx */
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acpigen_write_processor(core, pcontrol_blk, plen);
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/* Generate P-state tables */
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/* Generate C-state tables */
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/* Generate T-state tables */
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acpigen_pop_len();
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}
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}
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unsigned long acpi_madt_irq_overrides(unsigned long current)
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{
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int sci_irq = acpi_sci_irq();
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acpi_madt_irqoverride_t *irqovr;
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uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL;
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/* INT_SRC_OVR */
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irqovr = (acpi_madt_irqoverride_t *)current;
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current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
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if (sci_irq >= 20)
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sci_flags |= MP_IRQ_POLARITY_LOW;
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else
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sci_flags |= MP_IRQ_POLARITY_HIGH;
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irqovr = (acpi_madt_irqoverride_t *)current;
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current += acpi_create_madt_irqoverride(irqovr, 0, (u8)sci_irq, sci_irq,
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sci_flags);
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return current;
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}
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unsigned long southcluster_write_acpi_tables(device_t device,
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unsigned long current,
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struct acpi_rsdp *rsdp)
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{
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acpi_header_t *ssdt2;
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current = acpi_write_hpet(device, current, rsdp);
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current = (ALIGN(current, 16));
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ssdt2 = (acpi_header_t *)current;
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memset(ssdt2, 0, sizeof(acpi_header_t));
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acpi_create_serialio_ssdt(ssdt2);
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if (ssdt2->length) {
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current += ssdt2->length;
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acpi_add_table(rsdp, ssdt2);
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printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2,
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ssdt2->length);
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current = (ALIGN(current, 16));
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} else {
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ssdt2 = NULL;
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printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n");
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}
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printk(BIOS_DEBUG, "current = %lx\n", current);
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return current;
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}
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void southcluster_inject_dsdt(device_t device)
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{
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global_nvs_t *gnvs;
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gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (!gnvs) {
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gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
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if (gnvs)
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memset(gnvs, 0, sizeof(*gnvs));
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}
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if (gnvs) {
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acpi_create_gnvs(gnvs);
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acpi_save_gnvs((unsigned long)gnvs);
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/* And tell SMI about it */
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smm_setup_structures(gnvs, NULL, NULL);
|
||
|
|
|
||
|
|
/* Add it to DSDT. */
|
||
|
|
acpigen_write_scope("\\");
|
||
|
|
acpigen_write_name_dword("NVSA", (u32)gnvs);
|
||
|
|
acpigen_pop_len();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
__attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {}
|