50 lines
1.5 KiB
C
50 lines
1.5 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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struct southbridge_intel_i3100_config
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{
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#define I3100_GPIO_USE_MASK 0x03
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#define I3100_GPIO_USE_DEFAULT 0x00
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#define I3100_GPIO_USE_AS_NATIVE 0x01
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#define I3100_GPIO_USE_AS_GPIO 0x02
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#define I3100_GPIO_SEL_MASK 0x0c
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#define I3100_GPIO_SEL_DEFAULT 0x00
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#define I3100_GPIO_SEL_OUTPUT 0x04
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#define I3100_GPIO_SEL_INPUT 0x08
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#define I3100_GPIO_LVL_MASK 0x30
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#define I3100_GPIO_LVL_DEFAULT 0x00
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#define I3100_GPIO_LVL_LOW 0x10
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#define I3100_GPIO_LVL_HIGH 0x20
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#define I3100_GPIO_LVL_BLINK 0x30
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#define I3100_GPIO_INV_MASK 0xc0
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#define I3100_GPIO_INV_DEFAULT 0x00
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#define I3100_GPIO_INV_OFF 0x40
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#define I3100_GPIO_INV_ON 0x80
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/* GPIO use select */
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u8 gpio[64];
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u32 pirq_a_d;
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u32 pirq_e_h;
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};
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extern struct chip_operations southbridge_intel_i3100_ops;
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