2019-04-22 22:55:16 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* Copyright (C) 2017 Advanced Micro Devices
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/tsc.h>
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#include <console/console.h>
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2019-06-19 20:29:23 +02:00
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static unsigned long mhz;
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2019-04-22 22:55:16 +02:00
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unsigned long tsc_freq_mhz(void)
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{
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msr_t msr;
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uint8_t cpufid;
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uint8_t cpudid;
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2019-06-19 20:29:23 +02:00
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uint8_t high_state;
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2019-04-22 22:55:16 +02:00
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2019-06-19 20:29:23 +02:00
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if (mhz)
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return mhz;
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2019-04-22 22:55:16 +02:00
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2019-06-19 20:29:23 +02:00
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high_state = rdmsr(PS_LIM_REG).lo & 0x7;
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msr = rdmsr(PSTATE_0_MSR + high_state);
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2019-04-22 22:55:16 +02:00
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if (!(msr.hi & 0x80000000))
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die("Unknown error: cannot determine P-state 0\n");
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cpufid = (msr.lo & 0x3f);
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cpudid = (msr.lo & 0x1c0) >> 6;
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2019-06-19 20:29:23 +02:00
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mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
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return mhz;
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2019-04-22 22:55:16 +02:00
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}
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