coreboot-kgpe-d16/src/arch/riscv/Kconfig

config ARCH_BOOTBLOCK_RISCV
	bool
	default n
	select ARCH_RISCV

config ARCH_ROMSTAGE_RISCV
	bool
	default n

config ARCH_RAMSTAGE_RISCV
	bool
	default n

# If a custom bootblock is necessary, this option should be "select"-ed by
# the thing that needs it, probably the CPU.
config RISCV_BOOTBLOCK_CUSTOM
	bool
	default n

config CPU_HAS_BOOTBLOCK_INIT
	bool
	default n

config MAINBOARD_HAS_BOOTBLOCK_INIT
	bool
	default n
Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) 2014-11-26 20:25:47 +01:00			`config ARCH_BOOTBLOCK_RISCV`
			`bool`
			`default n`
			`select ARCH_RISCV`

			`config ARCH_ROMSTAGE_RISCV`
			`bool`
			`default n`

			`config ARCH_RAMSTAGE_RISCV`
			`bool`
			`default n`

			`# If a custom bootblock is necessary, this option should be "select"-ed by`
			`# the thing that needs it, probably the CPU.`
			`config RISCV_BOOTBLOCK_CUSTOM`
			`bool`
			`default n`

			`config CPU_HAS_BOOTBLOCK_INIT`
			`bool`
			`default n`

			`config MAINBOARD_HAS_BOOTBLOCK_INIT`
			`bool`
			`default n`