coreboot-kgpe-d16/src/include/device/pci.h

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/*
* PCI defines and function prototypes
* Copyright 1994, Drew Eckhardt
* Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
*
* For more information, please consult the following manuals (look at
* http://www.pcisig.com/ for how to get them):
*
* PCI BIOS Specification
* PCI Local Bus Specification
* PCI to PCI Bridge Specification
* PCI System Design Guide
*/
#ifndef PCI_H
#define PCI_H
#if CONFIG_PCI
#include <stdint.h>
Make the device tree available in the rom stage We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1398 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-01 01:47:25 +02:00
#include <stddef.h>
#include <rules.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/resource.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <device/pci_rom.h>
#ifndef __SIMPLE_DEVICE__
/* Common pci operations without a standard interface */
struct pci_operations {
/* set the Subsystem IDs for the PCI device */
void (*set_subsystem)(device_t dev, unsigned vendor, unsigned device);
};
/* Common pci bus operations */
struct pci_bus_operations {
uint8_t (*read8) (struct bus *pbus, int bus, int devfn, int where);
uint16_t (*read16) (struct bus *pbus, int bus, int devfn, int where);
uint32_t (*read32) (struct bus *pbus, int bus, int devfn, int where);
void (*write8) (struct bus *pbus, int bus, int devfn, int where, uint8_t val);
void (*write16) (struct bus *pbus, int bus, int devfn, int where, uint16_t val);
void (*write32) (struct bus *pbus, int bus, int devfn, int where, uint32_t val);
};
struct pci_driver {
const struct device_operations *ops;
unsigned short vendor;
unsigned short device;
const unsigned short *devices;
};
#define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver")))
/** start of compile time generated pci driver array */
extern struct pci_driver pci_drivers[];
/** end of compile time generated pci driver array */
extern struct pci_driver epci_drivers[];
extern struct device_operations default_pci_ops_dev;
extern struct device_operations default_pci_ops_bus;
void pci_dev_read_resources(device_t dev);
void pci_bus_read_resources(device_t dev);
void pci_dev_set_resources(device_t dev);
void pci_dev_enable_resources(device_t dev);
void pci_bus_enable_resources(device_t dev);
void pci_bus_reset(struct bus *bus);
device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn);
unsigned int do_pci_scan_bridge(device_t bus, unsigned int max,
unsigned int (*do_scan_bus)(struct bus *bus,
unsigned min_devfn, unsigned max_devfn, unsigned int max));
unsigned int pci_scan_bridge(device_t bus, unsigned int max);
unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max);
uint8_t pci_moving_config8(struct device *dev, unsigned reg);
uint16_t pci_moving_config16(struct device *dev, unsigned reg);
uint32_t pci_moving_config32(struct device *dev, unsigned reg);
struct resource *pci_get_resource(struct device *dev, unsigned long index);
void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device);
void pci_dev_init(struct device *dev);
unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev);
void pci_assign_irqs(unsigned bus, unsigned slot,
const unsigned char pIntAtoD[4]);
#define PCI_IO_BRIDGE_ALIGN 4096
#define PCI_MEM_BRIDGE_ALIGN (1024*1024)
static inline const struct pci_operations *ops_pci(device_t dev)
{
const struct pci_operations *pops;
pops = 0;
if (dev && dev->ops) {
pops = dev->ops->ops_pci;
}
return pops;
}
#endif /* ! __SIMPLE_DEVICE__ */
unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last);
unsigned pci_find_capability(device_t dev, unsigned cap);
void pci_early_bridge_init(void);
int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base);
#endif /* CONFIG_PCI */
#endif /* PCI_H */