367 lines
9.7 KiB
C
367 lines
9.7 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pnp.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/acpi.h>
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#include <pc80/i8254.h>
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#include <pc80/i8259.h>
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#include <soc/hudson.h>
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#include <vboot/vbnv.h>
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static void lpc_init(device_t dev)
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{
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u8 byte;
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u32 dword;
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device_t sm_dev;
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/* Enable the LPC Controller */
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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dword = pci_read_config32(sm_dev, 0x64);
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dword |= 1 << 20;
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pci_write_config32(sm_dev, 0x64, dword);
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/* Initialize isa dma */
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isa_dma_init();
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/* Enable DMA transaction on the LPC bus */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 2);
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pci_write_config8(dev, 0x40, byte);
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/* Disable the timeout mechanism on LPC */
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byte = pci_read_config8(dev, 0x48);
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byte &= ~(1 << 7);
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pci_write_config8(dev, 0x48, byte);
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/* Disable LPC MSI Capability */
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byte = pci_read_config8(dev, 0x78);
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byte &= ~(1 << 1);
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byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going
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on on LPC, it holds PCI grant, so no LPC slave cycle can
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interrupt and visit LPC. */
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pci_write_config8(dev, 0x78, byte);
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/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
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/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
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byte = pci_read_config8(dev, 0xBB);
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byte |= 1 << 0 | 1 << 3;
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pci_write_config8(dev, 0xBB, byte);
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cmos_check_update_date();
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/* Initialize the real time clock.
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* The 0 argument tells cmos_init not to
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* update CMOS unless it is invalid.
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* 1 tells cmos_init to always initialize the CMOS.
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*/
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if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS))
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init_vbnv_cmos(0);
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else
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cmos_init(0);
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/* Initialize i8259 pic */
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setup_i8259 ();
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/* Initialize i8254 timers */
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setup_i8254 ();
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/* Set up SERIRQ, enable continuous mode */
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byte = (BIT(4) | BIT(7));
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if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
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byte |= BIT(6);
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pm_write8(PM_SERIRQ_CONF, byte);
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}
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static void hudson_lpc_read_resources(device_t dev)
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{
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struct resource *res;
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/* Get the normal pci resources of this device */
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pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
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/* Add an extra subtractive resource for both memory and I/O. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->base = 0;
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res->size = 0x1000;
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->base = 0xff800000;
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res->size = 0x00800000; /* 8 MB for flash */
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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/* Add a memory resource for the SPI BAR. */
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fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
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res = new_resource(dev, 3); /* IOAPIC */
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res->base = IO_APIC_ADDR;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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compact_resources(dev);
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}
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static void hudson_lpc_set_resources(struct device *dev)
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{
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struct resource *res;
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u32 spi_enable_bits;
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/* Special case. The SpiRomEnable and other enables should STAY set. */
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res = find_resource(dev, 2);
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spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
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spi_enable_bits &= 0xF;
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pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits);
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pci_dev_set_resources(dev);
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}
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/**
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* @brief Enable resources for children devices
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*
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* @param dev the device whose children's resources are to be enabled
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*
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*/
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static void hudson_lpc_enable_childrens_resources(device_t dev)
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{
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struct bus *link;
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u32 reg, reg_x;
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int var_num = 0;
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u16 reg_var[3];
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u16 reg_size[1] = {512};
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u8 wiosize = pci_read_config8(dev, 0x74);
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/* Be bit relaxed, tolerate that LPC region might be bigger than resource we try to fit,
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* do it like this for all regions < 16 bytes. If there is a resource > 16 bytes
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* it must be 512 bytes to be able to allocate the fresh LPC window.
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*
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* AGESA likes to enable already one LPC region in wide port base 0x64-0x65,
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* using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size
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* The code tries to check if resource can fit into this region
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*/
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reg = pci_read_config32(dev, 0x44);
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reg_x = pci_read_config32(dev, 0x48);
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/* check if ranges are free and not use them if entry is just already taken */
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if (reg_x & (1 << 2))
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var_num = 1;
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/* just in case check if someone did not manually set other ranges too */
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if (reg_x & (1 << 24))
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var_num = 2;
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if (reg_x & (1 << 25))
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var_num = 3;
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/* check AGESA region size */
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if (wiosize & (1 << 0))
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reg_size[0] = 16;
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reg_var[2] = pci_read_config16(dev, 0x90);
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reg_var[1] = pci_read_config16(dev, 0x66);
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reg_var[0] = pci_read_config16(dev, 0x64);
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for (link = dev->link_list; link; link = link->next) {
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device_t child;
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for (child = link->children; child;
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child = child->sibling) {
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if (child->enabled
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&& (child->path.type == DEVICE_PATH_PNP)) {
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struct resource *res;
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for (res = child->resource_list; res; res = res->next) {
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u32 base, end; /* don't need long long */
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u32 rsize, set = 0, set_x = 0;
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if (!(res->flags & IORESOURCE_IO))
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continue;
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base = res->base;
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end = resource_end(res);
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/* find a resource size */
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printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n",
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dev_path(child), base, end);
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switch (base) {
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case 0x60: /* KB */
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case 0x64: /* MS */
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set |= (1 << 29);
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rsize = 1;
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break;
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case 0x3f8: /* COM1 */
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set |= (1 << 6);
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rsize = 8;
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break;
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case 0x2f8: /* COM2 */
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set |= (1 << 7);
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rsize = 8;
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break;
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case 0x378: /* Parallel 1 */
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set |= (1 << 0);
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set |= (1 << 1); /* + 0x778 for ECP */
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rsize = 8;
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break;
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case 0x3f0: /* FD0 */
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set |= (1 << 26);
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rsize = 8;
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break;
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case 0x220: /* 0x220 - 0x227 */
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set |= (1 << 8);
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rsize = 8;
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break;
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case 0x228: /* 0x228 - 0x22f */
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set |= (1 << 9);
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rsize = 8;
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break;
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case 0x238: /* 0x238 - 0x23f */
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set |= (1 << 10);
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rsize = 8;
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break;
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case 0x300: /* 0x300 -0x301 */
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set |= (1 << 18);
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rsize = 2;
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break;
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case 0x400:
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set_x |= (1 << 16);
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rsize = 0x40;
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break;
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case 0x480:
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set_x |= (1 << 17);
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rsize = 0x40;
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break;
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case 0x500:
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set_x |= (1 << 18);
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rsize = 0x40;
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break;
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case 0x580:
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set_x |= (1 << 19);
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rsize = 0x40;
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break;
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case 0x4700:
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set_x |= (1 << 22);
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rsize = 0xc;
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break;
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case 0xfd60:
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set_x |= (1 << 23);
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rsize = 16;
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break;
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default:
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rsize = 0;
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/* try AGESA allocated region in region 0 */
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if ((var_num > 0) && ((base >=reg_var[0]) &&
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((base + res->size) <= (reg_var[0] + reg_size[0]))))
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rsize = reg_size[0];
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}
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/* check if region found and matches the enable */
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if (res->size <= rsize) {
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reg |= set;
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reg_x |= set_x;
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/* check if we can fit resource in variable range */
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} else if ((var_num < 3) &&
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((res->size <= 16) || (res->size == 512))) {
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/* use variable ranges if pre-defined do not match */
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switch (var_num) {
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case 0:
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reg_x |= (1 << 2);
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if (res->size <= 16) {
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wiosize |= (1 << 0);
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}
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break;
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case 1:
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reg_x |= (1 << 24);
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if (res->size <= 16)
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wiosize |= (1 << 2);
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break;
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case 2:
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reg_x |= (1 << 25);
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if (res->size <= 16)
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wiosize |= (1 << 3);
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break;
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}
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reg_var[var_num++] =
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base & 0xffff;
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} else {
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printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n",
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dev_path(child), base, end);
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}
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}
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}
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}
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}
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pci_write_config32(dev, 0x44, reg);
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pci_write_config32(dev, 0x48, reg_x);
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/* Set WideIO for as many IOs found (fall through is on purpose) */
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switch (var_num) {
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case 3:
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pci_write_config16(dev, 0x90, reg_var[2]);
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/* fall through */
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case 2:
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pci_write_config16(dev, 0x66, reg_var[1]);
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/* fall through */
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case 1:
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pci_write_config16(dev, 0x64, reg_var[0]);
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break;
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}
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pci_write_config8(dev, 0x74, wiosize);
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}
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static void hudson_lpc_enable_resources(device_t dev)
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{
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pci_dev_enable_resources(dev);
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hudson_lpc_enable_childrens_resources(dev);
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}
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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/* Just a dummy */
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return current;
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations lpc_ops = {
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.read_resources = hudson_lpc_read_resources,
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.set_resources = hudson_lpc_set_resources,
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.enable_resources = hudson_lpc_enable_resources,
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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.write_acpi_tables = acpi_write_hpet,
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#endif
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.init = lpc_init,
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.scan_bus = scan_lpc_bus,
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.ops_pci = &lops_pci,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_AMD_SB900_LPC,
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PCI_DEVICE_ID_AMD_CZ_LPC,
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0
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};
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static const struct pci_driver lpc_driver __pci_driver = {
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.ops = &lpc_ops,
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.vendor = PCI_VENDOR_ID_AMD,
|
||
|
|
.devices = pci_device_ids,
|
||
|
|
};
|