162 lines
6.5 KiB
Plaintext
162 lines
6.5 KiB
Plaintext
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa/family14/root_complex
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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end
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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# device pci 18.0 on # northbridge
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chip northbridge/amd/agesa/family14 # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
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device pci 4.0 on end # PCIE P2P bridge on-board NIC
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device pci 5.0 off end # PCIE P2P bridge
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device pci 6.0 on end # PCIE P2P bridge PCIe slot
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device pci 7.0 off end # PCIE P2P bridge
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device pci 8.0 off end # NB/SB Link P2P bridge
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end # agesa northbridge
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chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # OHCI USB 0-4
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device pci 12.2 on end # EHCI USB 0-4
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device pci 13.0 on end # OHCI USB 5-9
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device pci 13.2 on end # EHCI USB 5-9
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device pci 14.0 on # SM
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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end # SM
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device pci 14.1 on end # IDE 0x439c
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on # LPC 0x439d
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chip superio/fintek/f81865f
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device pnp 4e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.3 off end # Parallel Port
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device pnp 4e.4 off end # Hardware Monitor
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device pnp 4e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 4e.6 off end # GPIO
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device pnp 4e.a off end # PME
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device pnp 4e.10 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.11 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end # f81865f
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end #LPC
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device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
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device pci 14.5 off end # OHCI FS/LS USB
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device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
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device pci 15.0 off end # PCIe PortA
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device pci 15.1 off end # PCIe PortB
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device pci 15.2 off end # PCIe PortC
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device pci 15.3 off end # PCIe PortD
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device pci 16.0 off end # OHCI USB 10-13
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device pci 16.2 off end # EHCI USB 10-13
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register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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#set up SB800 Fan control registers and IMC fan controls
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register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common
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register "fan0_enabled" = "1"
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register "fan1_enabled" = "1"
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register "imc_fan_zone0_enabled" = "1"
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register "imc_fan_zone1_enabled" = "1"
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register "fan0_config_vals" = "{ \
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FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
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FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
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register "fan1_config_vals" = "{ \
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FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
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FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
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register "imc_zone0_mode1" = " \
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IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
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IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
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register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
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IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
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register "imc_zone0_temp_offset" = "0x00" # No temp offset
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register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis
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register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address
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register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
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register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate
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register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping
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register "imc_zone1_mode1" = " \
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IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
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IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
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register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
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IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
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register "imc_zone1_temp_offset" = "0x00" # No temp offset
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register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis
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register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address
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register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
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register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate
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register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping
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# T56N has a Maximum operating temperature of 90C
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# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
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# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
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register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
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register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }"
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register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }"
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register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }"
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end #southbridge/amd/cimx/sb800
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# end # device pci 18.0
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# These seem unnecessary
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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device pci 18.6 on end
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device pci 18.7 on end
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register "spdAddrLookup" = "
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{
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{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
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{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
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}"
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end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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end #domain
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end #northbridge/amd/agesa/family14/root_complex
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