coreboot-kgpe-d16/util/romcc/results/linux_test5.out

min_cycle_time: 75 min_latency: 02
A
B
C
C
D
E
device: 00 new_cycle_time: 75 new_latency: 02
G
C
D
E
G
H
device: 00 new_cycle_time: 75 new_latency: 02
I
device: 00 min_cycle_time: 75 min_latency: 02
A
B
C
C
D
E
device: 01 new_cycle_time: 75 new_latency: 02
G
C
D
E
G
H
device: 01 new_cycle_time: 75 new_latency: 02
I
device: 01 min_cycle_time: 75 min_latency: 02
min_cycle_time: 75 min_latency: 02
- O2, enums, and switch statements work in romcc - Support for compiling romcc on non x86 platforms - new romc options -msse and -mmmx for specifying extra registers to use - Bug fixes to device the device disable/enable framework and an amd8111 implementation - Move the link specification to the chip specification instead of the path - Allow specifying devices with internal bridges. - Initial via epia support - Opteron errata fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2003-10-11 08:20:25 +02:00			`min_cycle_time: 75 min_latency: 02`
			`A`
			`B`
			`C`
			`C`
			`D`
			`E`
			`device: 00 new_cycle_time: 75 new_latency: 02`
			`G`
			`C`
			`D`
			`E`
			`G`
			`H`
			`device: 00 new_cycle_time: 75 new_latency: 02`
			`I`
			`device: 00 min_cycle_time: 75 min_latency: 02`
			`A`
			`B`
			`C`
			`C`
			`D`
			`E`
			`device: 01 new_cycle_time: 75 new_latency: 02`
			`G`
			`C`
			`D`
			`E`
			`G`
			`H`
			`device: 01 new_cycle_time: 75 new_latency: 02`
			`I`
			`device: 01 min_cycle_time: 75 min_latency: 02`
			`min_cycle_time: 75 min_latency: 02`