2018-02-10 03:35:17 +01:00
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FLASH 16M {
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WP_RO@0x0 0x400000 {
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SI_DESC@0x0 0x1000
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IFWI@0x1000 0x1ff000
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RO_VPD@0x200000 0x4000
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RO_SECTION@0x204000 0x1fc000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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2018-07-20 08:00:04 +02:00
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COREBOOT(CBFS)@0x1000 0x1bb000
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GBB@0x1bc000 0x40000
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2018-02-10 03:35:17 +01:00
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}
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}
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MISC_RW@0x400000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x21000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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RW_VAR_MRC_CACHE@0x20000 0x1000
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}
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RW_ELOG@0x21000 0x3000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD@0x28000 0x2000
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RW_NVRAM@0x2a000 0x5000
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FPF_STATUS@0x2f000 0x1000
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}
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RW_SECTION_A@0x430000 0x480000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x46ffc0
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RW_FWID_A@0x47ffc0 0x40
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}
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RW_SECTION_B@0x8b0000 0x480000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x46ffc0
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RW_FWID_B@0x47ffc0 0x40
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}
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RW_LEGACY(CBFS)@0xd30000 0x200000
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BIOS_UNUSABLE@0xf30000 0x4f000
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DEVICE_EXTENSION@0xf7f000 0x80000
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# Currently, it is required that the BIOS region be a multiple of 8KiB.
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# This is required so that the recovery mechanism can find SIGN_CSE
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# region aligned to 4K at the center of BIOS region. Since the
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# descriptor at the beginning uses 4K and BIOS starts at an offset of
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# 4K, a hole of 4K is created towards the end of the flash to compensate
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# for the size requirement of BIOS region.
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# FIT tool thus creates descriptor with following regions:
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# Descriptor --> 0 to 4K
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# BIOS --> 4K to 0xf7f000
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# Device ext --> 0xf7f000 to 0xfff000
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UNUSED_HOLE@0xfff000 0x1000
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}
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