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Documentation/soc/intel: Add documentation for Intel FSP This patch combines open source documentation for Intel FSP specification. Change-Id: I3a8bc0198a1e01ec019139b728834713978501ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31838 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-11 11:10:00 +01:00
# Intel Firmware Support Package (FSP)-specific documentation
This section contains documentation about Intel-FSP in public domain.
Documentation: Add FSP bugs As Intel doesn't even document known bugs add a list of FSP bugs here. Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 16:21:15 +02:00
## Bugs
As Intel doesn't even list known bugs, they are collected here until
those are fixed. If possible a workaround is described here as well.
### BroadwellDEFsp
* IA32_FEATURE_CONTROL MSR is locked in FSP-M
* Release MR2
* Writing the MSR is required in ramstage for Intel TXT
* Workaround: none
* Issue on public tracker: [Issue 10]
* FSP-S asserts if the thermal PCI device 00:1f.6 is disabled
* Release MR2
* FSP expects the PCI device to be enabled
* FSP expects BARs to be properly assigned
* Workaround: Don't disable this PCI device
* Issue on public tracker: [Issue 13]
### KabylakeFsp
* MfgId and ModulePartNum in the DIMM_INFO struct are empty
* Release 3.7.1
* Those values are typically consumed by SMBIOS type 17
* Workaround: none
* Issue on public tracker: [Issue 22]
### BraswellFsp
* Internal UART can't be disabled using PcdEnableHsuart*
* Release MR2
* Workaround: Disable internal UART manually after calling FSP
* Issue on public tracker: [Issue 10]
Documentation/soc/intel: Add documentation for Intel FSP This patch combines open source documentation for Intel FSP specification. Change-Id: I3a8bc0198a1e01ec019139b728834713978501ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31838 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-11 11:10:00 +01:00
## Open Source Intel FSP specification
* [About Intel FSP](https://firmware.intel.com/learn/fsp/about-intel-fsp)
* [FSP Specification 1.0](https://www.intel.in/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf)
* [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf)
* [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf)
Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI Some new feature added into FSP specification to perform dispatching of external PPI service from boot firmware (coreboot) to FSP. Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-11 11:31:20 +01:00
Documentation/soc/intel/fsp: Add link for external FSP2.1 spec Change-Id: I5d1abd6252bda2be09285cd878a483f055abcd7b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35238 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-03 12:49:30 +02:00
* [FSP Specification 2.1](https://cdrdv2.intel.com/v1/dl/getContent/611786)
Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI Some new feature added into FSP specification to perform dispatching of external PPI service from boot firmware (coreboot) to FSP. Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-11 11:31:20 +01:00
## Additional Features in FSP 2.1 specification
- [PPI](ppi/ppi.md)
Documentation: Add FSP bugs As Intel doesn't even document known bugs add a list of FSP bugs here. Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 16:21:15 +02:00
## Official bugtracker
- [IntelFSP/FSP](https://github.com/IntelFsp/FSP/issues)
[Issue 10]: https://github.com/IntelFsp/FSP/issues/10
[Issue 13]: https://github.com/IntelFsp/FSP/issues/13
[Issue 15]: https://github.com/IntelFsp/FSP/issues/15
[Issue 22]: https://github.com/IntelFsp/FSP/issues/22