coreboot-kgpe-d16/src/arch/arm64/id.S

#include <build.h>

	.section ".id", "a", %progbits

	.globl __id_start
__id_start:
ver:
	.asciz COREBOOT_VERSION
vendor:
	.asciz CONFIG_MAINBOARD_VENDOR
part:
	.asciz CONFIG_MAINBOARD_PART_NUMBER
.long __id_end - ver  /* Reverse offset to the vendor id */
.long __id_end - vendor  /* Reverse offset to the vendor id */
.long __id_end - part    /* Reverse offset to the part number */
.long CONFIG_ROM_SIZE                               /* Size of this romimage */
	.globl __id_end

__id_end:
.previous
coreboot arm64: Add support for arm64 into coreboot framework Add support for enabling different coreboot stages (bootblock, romstage and ramstage) to have arm64 architecture. Most of the files have been copied over from arm/ or arm64-generic work. Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/197397 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 033ba96516805502673ac7404bc97e6ce4e2a934) This patch is essentially a squash of aarch64 changes made by these patches: d955885 coreboot: Rename coreboot_ram stage to ramstage a492761 cbmem console: Locate the preram console with a symbol instead of a sect 96e7f0e aarch64: Enable early icache and migrate SCTLR from EL3 3f854dc aarch64: Pass coreboot table in jmp_to_elf_entry ab3ecaf aarch64/foundation-armv8: Set up RAM area and enter ramstage 25fd2e9 aarch64: Remove CAR definitions from early_variables.h 65bf77d aarch64/foundation-armv8: Enable DYNAMIC_CBMEM 9484873 aarch64: Change default exception level to EL2 7a152c3 aarch64: Fix formatting of exception registers dump 6946464 aarch64: Implement basic exception handling c732a9d aarch64/foundation-armv8: Basic bootblock implementation 3bc412c aarch64: Comment out some parts of code to allow build ab5be71 Add initial aarch64 support The ramstage support is the only portion that has been tested on actual hardware. Bootblock and romstage support may require modifications to run on hardware. Change-Id: Icd59bec55c963a471a50e30972a8092e4c9d2fb2 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6915 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Furquan Shaikh <furquan@google.com> 2014-04-29 01:39:40 +02:00			`#include <build.h>`

			`.section ".id", "a", %progbits`

			`.globl __id_start`
			`__id_start:`
			`ver:`
			`.asciz COREBOOT_VERSION`
			`vendor:`
			`.asciz CONFIG_MAINBOARD_VENDOR`
			`part:`
			`.asciz CONFIG_MAINBOARD_PART_NUMBER`
			`.long __id_end - ver /* Reverse offset to the vendor id */`
			`.long __id_end - vendor /* Reverse offset to the vendor id */`
			`.long __id_end - part /* Reverse offset to the part number */`
			`.long CONFIG_ROM_SIZE /* Size of this romimage */`
			`.globl __id_end`

			`__id_end:`
			`.previous`