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coreboot-kgpe-d16/src/include/device/pci_rom.h

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onboard pci_rom git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13 19:42:22 +01:00
#ifndef PCI_ROM_H
#define PCI_ROM_H
Unify byte order macros and clrsetbits This patch removes quite a bit of code duplication between cpu_to_le32() and clrsetbits_le32() style macros on the different architectures. This also syncs those macros back up to the new write32(a, v) style IO accessor macros that are now used on ARM and ARM64. CQ-DEPEND=CL:254862 BRANCH=none BUG=chromium:444723 TEST=Compiled Cosmos, Daisy, Blaze, Falco, Pinky, Pit, Rambi, Ryu, Storm and Urara. Booted on Jerry. Tried to compare binary images... unfortunately something about the new macro notation makes the compiler evaluate it more efficiently (not recalculating the address between the read and the write), so this was of limited value. Change-Id: If8ab62912c952d68a67a0f71e82b038732cd1317 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd43bf446581bfb84bec4f2ebb56b5de95971c3b Original-Change-Id: I7d301b5bb5ac0db7f5ff39e3adc2b28a1f402a72 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254866 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-23 23:31:09 +01:00
#include <endian.h>
added PCI expansion ROM support, works for some ATI and Nvidia AGP cards now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-11 00:16:22 +01:00
#include <stddef.h>
x86/acpi: Add VFCT table Add VFCT table to provide PCI Optiom Rom for AMD graphic devices. Useful for GNU Linux payloads and embedded dual GPU systems. Tested on Lenovo T500 with AMD RV635 as secondary gpu. Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 Reviewed-on: https://review.coreboot.org/18192 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-31 20:04:23 +02:00
#include <arch/acpi.h>
added PCI expansion ROM support, works for some ATI and Nvidia AGP cards now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-11 00:16:22 +01:00
#define PCI_ROM_HDR 0xAA55
src/include: Remove spaces before ( and after ) Fix the following error messages found by checkpatch.pl: ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' TEST=Build and run on Galileo Gen2 Change-Id: I2a9a0df640c51ff3efa83dde852dd6ff37ac3c06 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18651 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07 23:31:19 +01:00
#define PCI_DATA_HDR ((uint32_t) (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P'))
added PCI expansion ROM support, works for some ATI and Nvidia AGP cards now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-11 00:16:22 +01:00
#define PCI_RAM_IMAGE_START 0xD0000
#define PCI_VGA_RAM_IMAGE_START 0xC0000
struct rom_header {
uint16_t signature;
uint8_t size;
uint8_t init[3];
uint8_t reserved[0x12];
uint16_t data;
};
struct pci_data {
uint32_t signature;
uint16_t vendor;
uint16_t device;
uint16_t reserved_1;
uint16_t dlen;
uint8_t drevision;
class code reverse git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-18 04:10:46 +01:00
uint8_t class_lo;
uint16_t class_hi;
added PCI expansion ROM support, works for some ATI and Nvidia AGP cards now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-11 00:16:22 +01:00
uint16_t ilen;
uint16_t irevision;
uint8_t type;
uint8_t indicator;
uint16_t reserved_2;
};
onboard pci_rom git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13 19:42:22 +01:00
Fix a redundant declaration warning (trivial) src/include/device/pci.h:75: warning: redundant redeclaration of 'pci_dev_init' src/include/device/pci_rom.h:39: warning: previous declaration of 'pci_dev_init' was here Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-22 03:42:13 +02:00
struct rom_header *pci_rom_probe(struct device *dev);
src/include: Wrap lines at 80 columns Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters Changed a few comments to reduce line length. File src/include/cpu/amd/vr.h was skipped. TEST=Build and run on Galileo Gen2 Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18687 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-08 02:45:12 +01:00
struct rom_header *pci_rom_load(struct device *dev,
struct rom_header *rom_header);
x86/acpi: Add VFCT table Add VFCT table to provide PCI Optiom Rom for AMD graphic devices. Useful for GNU Linux payloads and embedded dual GPU systems. Tested on Lenovo T500 with AMD RV635 as secondary gpu. Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 Reviewed-on: https://review.coreboot.org/18192 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-31 20:04:23 +02:00
unsigned long
pci_rom_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp);
device/pci_rom: Write _ROM method for VGA devices Write _ROM method and store PCI Option ROM in CBMEM. Allows an EFI compatible OS to retrieve the Option ROM without the need to access the PCI BAR. As the Option ROM is no longer present in the legacy VGA area it's required for mobile platforms. On hybrid devices, like Lenovo Thinkpads supporting NVIDIA Optimus it's the only way to retrieve the Option ROM, even with legacy BIOS, as there's no PCI BAR to map. Tested on: * Lenovo T530 * Linux Kernel 4.13.7 * nouveau Change-Id: I548b730fb64833083cc05af5b21dd6959804224b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-06 19:30:55 +02:00
void pci_rom_ssdt(struct device *device);
Rework map_oprom_vendev to add revision check and mapping AMD's Family 17h SoCs share the same video device ID, but may need different video BIOSes. This adds the common code changes to check the vendor & device IDs along with the revision and select the correct video BIOS to use. Change-Id: I2978a5693c904ddb09d23715cb309c4a356e0370 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2040455 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-02-06 00:46:30 +01:00
void map_oprom_vendev_rev(u32 *vendev, u8 *rev);
RELOCATABLE_RAMSTAGE: Fix weak symbols with option ROMs After relocation the weak symbol map_oprom_vendev is no longer NULL. Always have empty stub function defined. Change-Id: I5b1bdeb3f37bb04363cf3d9dedaeafc9e193aaae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7956 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-26 12:29:09 +01:00
u32 map_oprom_vendev(u32 vendev);
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-10 Creator: Yinghai Lu <yhlu@tyan.com> pci_rom.h smbus device parent device print git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06 18:49:59 +02:00
device/pci_device.c: Use verified boot to check oprom Before oprom is executed, no check is performed if rom passes verification. Add call to verified_boot_should_run_oprom() to verify the oprom. verified_boot_should_run_oprom() expects and rom address as input pointer. *rom is added as input parameter to should_run_oprom() which must be parsed to verified_boot_should_run_oprom().. BUG=N/A TEST=Created verified binary and verify logging on Facebook FBG1701 Change-Id: Iec5092e85d34940ea3a3bb1192ea49f3bc3e5b27 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-04 14:06:33 +02:00
int verified_boot_should_run_oprom(struct rom_header *rom_header);
onboard pci_rom git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13 19:42:22 +01:00
#endif
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