2013-08-13 11:09:51 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Advanced Micro Devices, Inc.
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* Copyright (C) 2013 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* DefinitionBlock Statement */
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DefinitionBlock (
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"DSDT.AML", /* Output filename */
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"DSDT", /* Signature */
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0x02, /* DSDT Revision, needs to be 2 for 64bit */
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"AMD ", /* OEMID */
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"COREBOOT", /* TABLE ID */
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
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/* Globals for the platform */
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#include "acpi/mainboard.asl"
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/* Describe the USB Overcurrent pins */
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#include "acpi/usb_oc.asl"
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/* PCI IRQ mapping for the Southbridge */
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#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
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/* Describe the processor tree (\_PR) */
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#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
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/* Contains the supported sleep states for this chipset */
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#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
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/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
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#include "acpi/sleep.asl"
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/* System Bus */
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Scope(\_SB) { /* Start \_SB scope */
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
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#include "acpi/routing.asl"
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2014-04-18 08:42:19 +02:00
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Device(PWRB) {
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Name(_HID, EISAID("PNP0C0C"))
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Name(_UID, 0xAA)
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Name(_PRW, Package () {3, 0x04})
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Name(_STA, 0x0B)
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}
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2013-08-13 11:09:51 +02:00
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Device(PCI0) {
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/* Describe the AMD Northbridge */
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#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
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/* Describe the AMD Fusion Controller Hub Southbridge */
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#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
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}
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/* Describe PCI INT[A-H] for the Southbridge */
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#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
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} /* End \_SB scope */
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/* Describe SMBUS for the Southbridge */
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#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
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/* Define the General Purpose Events for the platform */
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#include "acpi/gpe.asl"
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/* Define the Thermal zones and methods for the platform */
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#include "acpi/thermal.asl"
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/* Define the System Indicators for the platform */
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#include "acpi/si.asl"
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}
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/* End of ASL file */
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