84 lines
2.5 KiB
C
84 lines
2.5 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#include <device/pci_def.h>
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#include <arch/acpi.h>
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#include "gm45.h"
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void init_iommu()
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{
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/* FIXME: proper test? */
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int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff;
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int stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION);
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MCHBAR32(0x28) = IOMMU_BASE1 | 1; /* HDA @ 0:1b.0 */
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if (stepping != STEPPING_B2) {
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/* The official workaround is to run SMM every 64ms.
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The only winning move is not to play. */
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MCHBAR32(0x18) = IOMMU_BASE2 | 1; /* IGD @ 0:2.0-1 */
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} else {
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/* write-once, so lock it down */
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MCHBAR32(0x18) = 0; /* disable IOMMU for IGD @ 0:2.0-1 */
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}
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if (me_active) {
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MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */
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}
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MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */
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/* clear GTT */
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u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
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if (gtt & 0x400) { /* VT mode */
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device_t igd = PCI_DEV(0, 2, 0);
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/* setup somewhere */
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u8 cmd = pci_read_config8(igd, PCI_COMMAND);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config8(igd, PCI_COMMAND, cmd);
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void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
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/* clear GTT, 2MB is enough (and should be safe) */
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memset(bar, 0, 2<<20);
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/* and now disable again */
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cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config8(igd, PCI_COMMAND, cmd);
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pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0);
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}
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if (stepping == STEPPING_B3) {
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MCHBAR8(0xffc) |= 1 << 4;
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device_t peg = PCI_DEV(0, 1, 0);
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/* FIXME: proper test? */
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if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) {
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int val = pci_read_config32(peg, 0xfc) | (1 << 15);
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pci_write_config32(peg, 0xfc, val);
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}
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}
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/* final */
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MCHBAR8(0x94) |= 1 << 3;
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}
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