51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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#include <soc/bootblock.h>
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#include <soc/pmc.h>
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#include <console/console.h>
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#define PCR_DMI_DMICTL 0x2234
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#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
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#define PCR_DMI_ACPIBA 0x27B4
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#define PCR_DMI_ACPIBDID 0x27B8
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#define PCR_DMI_PMBASEA 0x27AC
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#define PCR_DMI_PMBASEC 0x27B0
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static void soc_config_acpibase(void)
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{
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uint32_t reg32;
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/* Disable ABASE in PMC Device first before changing Base Address */
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reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
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pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);
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/* Program ACPI Base */
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pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
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/* Enable ACPI in PMC */
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pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);
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uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE);
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printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data);
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/*
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* Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]
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* to [0x3F, PMC PCI Offset 40h bit[15:2], 1]
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*/
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reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1;
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pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
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pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
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}
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void bootblock_pch_init(void)
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{
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/*
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* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT
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*/
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soc_config_acpibase();
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}
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