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coreboot-kgpe-d16/src/soc/amd/picasso/smu.c

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soc/amd/picasso: Add generic SMU service request Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-23 14:43:44 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
#include <timer.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/smu.h>
#include <types.h>
static uint32_t smu_read32(uint32_t reg)
{
pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg);
return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR);
}
static void smu_write32(uint32_t reg, uint32_t val)
{
pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg);
pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val);
}
#define SMU_MESG_RESP_TIMEOUT 0x00
#define SMU_MESG_RESP_OK 0x01
/* returns SMU_MESG_RESP_OK, SMU_MESG_RESP_TIMEOUT or a negative number */
soc/amd/picasso/smu: only print time for actual command execution When waiting for the SMU to be ready to accept a new command, the time spent waiting shouldn't be printed as command execution time. Also fix the time unit in the print statement. Change-Id: I6b97b11cd9efae7029779ee2096d4f2224cecd72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-26 23:31:56 +02:00
static int32_t smu_poll_response(bool print_command_duration)
soc/amd/picasso: Add generic SMU service request Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-23 14:43:44 +02:00
{
struct stopwatch sw;
const long timeout_ms = 10 * MSECS_PER_SEC;
int32_t result;
stopwatch_init_msecs_expire(&sw, timeout_ms);
do {
result = smu_read32(REG_ADDR_MESG_RESP);
if (result) {
soc/amd/picasso/smu: only print time for actual command execution When waiting for the SMU to be ready to accept a new command, the time spent waiting shouldn't be printed as command execution time. Also fix the time unit in the print statement. Change-Id: I6b97b11cd9efae7029779ee2096d4f2224cecd72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-26 23:31:56 +02:00
if (print_command_duration)
printk(BIOS_SPEW, "SMU command consumed %ld usecs\n",
soc/amd/picasso: Add generic SMU service request Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-23 14:43:44 +02:00
stopwatch_duration_usecs(&sw));
return result;
}
} while (!stopwatch_expired(&sw));
printk(BIOS_ERR, "Error: timeout sending SMU message\n");
return SMU_MESG_RESP_TIMEOUT;
}
/*
* Send a message and bi-directional payload to the SMU. SMU response, if any, is returned via
* arg.
*/
enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg)
{
size_t i;
/* wait until SMU can process a new request; don't care if an old request failed */
soc/amd/picasso/smu: only print time for actual command execution When waiting for the SMU to be ready to accept a new command, the time spent waiting shouldn't be printed as command execution time. Also fix the time unit in the print statement. Change-Id: I6b97b11cd9efae7029779ee2096d4f2224cecd72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-26 23:31:56 +02:00
if (smu_poll_response(false) == SMU_MESG_RESP_TIMEOUT)
soc/amd/picasso: Add generic SMU service request Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-23 14:43:44 +02:00
return CB_ERR;
/* clear response register */
smu_write32(REG_ADDR_MESG_RESP, 0);
/* populate arguments */
for (i = 0 ; i < SMU_NUM_ARGS ; i++)
smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]);
/* send message to SMU */
smu_write32(REG_ADDR_MESG_ID, id);
/* wait until SMU has processed the message and check if it was successful */
soc/amd/picasso/smu: only print time for actual command execution When waiting for the SMU to be ready to accept a new command, the time spent waiting shouldn't be printed as command execution time. Also fix the time unit in the print statement. Change-Id: I6b97b11cd9efae7029779ee2096d4f2224cecd72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-26 23:31:56 +02:00
if (smu_poll_response(true) != SMU_MESG_RESP_OK)
soc/amd/picasso: Add generic SMU service request Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-23 14:43:44 +02:00
return CB_ERR;
/* copy returned values */
for (i = 0 ; i < SMU_NUM_ARGS ; i++)
arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i));
return CB_SUCCESS;
}
/*
* Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and
* SlpTypeEn is clear. Function does not return if successful.
*/
void smu_sx_entry(void)
{
struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */
printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n");
send_smu_message(SMC_MSG_S3ENTRY, &msg);
}
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