2004-10-14 22:13:01 +02:00
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#ifndef CPU_AMD_MTRR_H
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#define CPU_AMD_MTRR_H
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#define IORR_FIRST 0xC0010016
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#define IORR_LAST 0xC0010019
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#define MTRR_READ_MEM (1 << 4)
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#define MTRR_WRITE_MEM (1 << 3)
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#define SYSCFG_MSR 0xC0010010
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#define SYSCFG_MSR_TOM2En (1 << 21)
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#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
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#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
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#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
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#define SYSCFG_MSR_UcLockEn (1 << 17)
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#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
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#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
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#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
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#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
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#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
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#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
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#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
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2010-10-12 08:13:40 +02:00
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#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
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#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
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#define TOP_MEM_MSR 0xC001001A
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#define TOP_MEM2_MSR 0xC001001D
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#define TOP_MEM TOP_MEM_MSR
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#define TOP_MEM2 TOP_MEM2_MSR
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2004-10-14 22:13:01 +02:00
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#define TOP_MEM_MASK 0x007fffff
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#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
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2010-03-28 23:26:54 +02:00
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#if !defined(__PRE_RAM__) && !defined(ASSEMBLY)
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2004-10-14 22:13:01 +02:00
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void amd_setup_mtrrs(void);
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2010-03-28 23:26:54 +02:00
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#endif
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2004-10-14 22:13:01 +02:00
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#endif /* CPU_AMD_MTRR_H */
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