284 lines
9.6 KiB
Markdown
284 lines
9.6 KiB
Markdown
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# Gigabyte GA-G41M-ES2L rev 1.1
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This page describes how to use coreboot on the [Gigabyte GA-G41M-ES2L rev 1.1](https://www.gigabyte.com/Motherboard/GA-G41M-ES2L-rev-11) mainboard.
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This motherboard [also works with Libreboot](https://libreboot.org/docs/install/ga-g41m-es2l.html).
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Type | Value |
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+==================+==================================================+
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| BIOS flash chips | 2 x SST25VF080B (8 Mbit SPI) (DUAL BIOS) |
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+------------------+--------------------------------------------------+
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| Northbridge | Intel G41 |
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+------------------+--------------------------------------------------+
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| Southbridge | Intel ICH7 |
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+------------------+--------------------------------------------------+
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| CPU socket | LGA775 |
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+------------------+--------------------------------------------------+
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| RAM | 2 x DDR2 800, max. 8 GiB |
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+------------------+--------------------------------------------------+
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| SuperIO | ITE IT8718F-S |
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+------------------+--------------------------------------------------+
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| Audio | Realtek ALC888B |
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+------------------+--------------------------------------------------+
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| Network | Realtek RTL8111C PCIe Gigabit Ethernet |
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+------------------+--------------------------------------------------+
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```
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## Preparation
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```eval_rst
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For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`.
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```
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### Devuan 4 Chimaera
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This probably works also for any fresh Debian/Ubuntu-based distros.
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Install tools and libraries needed for coreboot:
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```shell
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sudo apt-get -V install bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev wget python2 python-is-python2 flashrom
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```
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### Get sources
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You need about 700 MB disk space for sources only and ~2GB disk space for sources + build results
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```shell
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git clone --recursive https://review.coreboot.org/coreboot.git
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```
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### Build toolchain
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Your system compilers can be different with versions, tested by coreboot developers.
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So, it is recommended to build cross-compilers with special versions, which were tested with coreboot.
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It is possible to skip this time-consuming part and use `ANY_TOOLCHAIN=y`, but this not recommended.
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You can build them for all platforms: `make crossgcc CPUS=2` but this takes ~2 hours with Intel core2duo E8400.
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The best way, probably, is to build cross-compilers for your platform (this takes ~20 minutes with Intel core2duo E8400):
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```shell
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make crossgcc-i386 CPUS=2
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```
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### Save MAC-address of internal LAN
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Run `ip -c link show`, you will find MAC-address like 6c:f0:49:xx:xx:xx
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```
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1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
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link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
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2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000
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link/ether 6c:f0:49:xx:xx:xx brd ff:ff:ff:ff:ff:ff
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```
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## Configure
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Create file `payloads/external/SeaBIOS/.config_seabios`:
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```shell
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CONFIG_COREBOOT=y
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CONFIG_ATA_DMA=y
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CONFIG_VGA_COREBOOT=y
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```
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Edit file `configs/config.gigabyte_ga-g41m-es2l`, replace `CONFIG_REALTEK_8168_MACADDRESS` value with your MAC-address.
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Run
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```shell
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make defconfig KBUILD_DEFCONFIG="configs/config.gigabyte_ga-g41m-es2l"
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```
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## Build
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Just execute:
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```shell
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make
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```
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It takes ~2 minutes with Intel core2duo E8400.
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Example of last part in the output:
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```
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CBFSPRINT coreboot.rom
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FMAP REGION: COREBOOT
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Name Offset Type Size Comp
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cbfs master header 0x0 cbfs header 32 none
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fallback/romstage 0x80 stage 62316 none
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cpu_microcode_blob.bin 0xf480 microcode 180224 none
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fallback/ramstage 0x3b500 stage 98745 none
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vgaroms/seavgabios.bin 0x53700 raw 28672 none
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config 0x5a740 raw 301 none
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revision 0x5a8c0 raw 675 none
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build_info 0x5abc0 raw 103 none
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fallback/dsdt.aml 0x5ac80 raw 8447 none
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rt8168-macaddress 0x5cdc0 raw 17 none
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vbt.bin 0x5ce40 raw 802 LZMA (1899 decompressed)
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cmos.default 0x5d1c0 cmos_default 256 none
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cmos_layout.bin 0x5d300 cmos_layout 1040 none
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fallback/postcar 0x5d740 stage 20844 none
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fallback/payload 0x62900 simple elf 70270 none
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payload_config 0x73bc0 raw 1699 none
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payload_revision 0x742c0 raw 237 none
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(empty) 0x74400 null 482904 none
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bootblock 0xea280 bootblock 23360 none
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HOSTCC cbfstool/ifwitool.o
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HOSTCC cbfstool/ifwitool (link)
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Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
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```
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## Flashing coreboot
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```eval_rst
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In addition to the information here, please see the
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:doc:`../../flash_tutorial/index`.
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```
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### Do backup
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The above commands read the SPI flash chip(s), write into file and then verify content again with the chip:
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```shell
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sudo flashrom -p internal:dualbiosindex=0 -r m_bios.rom
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sudo flashrom -p internal:dualbiosindex=0 -v m_bios.rom
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sudo flashrom -p internal:dualbiosindex=1 -r b_bios.rom
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sudo flashrom -p internal:dualbiosindex=1 -v b_bios.rom
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```
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If access error appeared, then add `iomem=relaxed` to Linux kernel parameters and restart your Linux system.
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You can also repeat backup and compare checksums manually.
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Backup file should be stored elsewhere, so that in case the coreboot build is faulty, some external procedure can be used without having to extract the backup from the target device first.
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### Write new flash image
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Let's write new image into SPI flash chip, verify checksum again and erase second flash chip:
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```shell
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sudo flashrom -p internal:dualbiosindex=0 -w build/coreboot.rom
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sudo flashrom -p internal:dualbiosindex=0 -v build/coreboot.rom
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sudo flashrom -p internal:dualbiosindex=1 -E
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```
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## Set text mode for GRUB
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Update your `/etc/default/grub` with:
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```shell
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GRUB_TERMINAL=console
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```
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And recreate GRUB configuration `/boot/grub/grub.cfg` by command
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```shell
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sudo update-grub
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```
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## Boot with new firmware
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Restart your system:
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```shell
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sudo shutdown -r now
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```
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If it is needed, use <kbd>Esc</kbd> key to choose boot device.
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Remove `iomem=relaxed` from Linux kernel parameters.
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Enjoy!
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## Status
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```
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+-----------------------+--------------------------+--------+-------------------------------+
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| coreboot version | Date of sources checkout | Status | Comment |
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+-----------------------+--------------------------+--------+-------------------------------+
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| 4.13-1531-g2fae1c0494 | 2021-01-28 | Good | |
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+-----------------------+--------------------------+--------+-------------------------------+
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| 4.13-2182-g6410a0002f | 2021-02-18 | Good | |
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+-----------------------+--------------------------+--------+-------------------------------+
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```
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### Known issues
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Lm-sensors shows wrong values from it87:
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```
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coretemp-isa-0000
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Adapter: ISA adapter
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Core 0: +27.0°C (high = +80.0°C, crit = +100.0°C)
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Core 1: +31.0°C (high = +80.0°C, crit = +100.0°C)
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it8718-isa-0290
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Adapter: ISA adapter
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in0: 1.06 V (min = +0.00 V, max = +4.08 V)
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in1: 1.90 V (min = +0.00 V, max = +4.08 V)
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in2: 3.34 V (min = +0.00 V, max = +4.08 V)
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+5V: 2.96 V (min = +0.00 V, max = +4.08 V)
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in4: 224.00 mV (min = +0.00 V, max = +4.08 V)
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in5: 4.08 V (min = +0.00 V, max = +4.08 V) ALARM
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in6: 4.08 V (min = +0.00 V, max = +4.08 V) ALARM
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in7: 3.09 V (min = +0.00 V, max = +4.08 V)
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Vbat: 2.82 V
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fan1: 1290 RPM (min = 0 RPM)
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fan2: 0 RPM (min = 0 RPM)
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temp1: -54.0°C (low = +0.0°C, high = +127.0°C) sensor = thermistor
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temp2: -1.0°C (low = +0.0°C, high = +127.0°C) sensor = thermistor
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temp3: +44.0°C (low = +0.0°C, high = +127.0°C) sensor = thermal diode
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cpu0_vid: +1.100 V
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intrusion0: ALARM
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```
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### Working
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- RAM 1,2x1GiB DDR2 PC2-6400 Kingston KTC1G-UDIMM (1.8V, 2Rx8 ?)
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- RAM 1x1GiB DDR2 PC2-5300 Brooktree AU1G08E32-667P005 / Apogee AU1G082-667P005 CL6 (1.8V, 2Rx8 ?)
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- CPU E8400
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- ACPI
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- CPU frequency scaling
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- flashrom under coreboot
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- Gigabit Ethernet
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- Hardware monitoring
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- Integrated graphics
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- SATA
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- PCI POST card
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### Not working
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- SuperIO based fan control: PWM fan speed is not changing in depend of CPU temperature
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- RAM 1,2x4GiB DDR2 PC2-6400 Samsung M378T5263AZ3-CF7 (2Rx4 PC2-6400U-666-12-E3)
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### Not tested
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- KVM virtualization
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- Onboard audio
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- PCI
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- PCIe
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- PS/2 keyboard mouse (during payload, bootloader)
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- Serial port
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- USB (disabling XHCI controller makes to work as fallback USB2.0 ports)
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- IOMMU
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## Interesting facts
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`lshw` output is different for BIOS and coreboot.
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```shell
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diff --side-by-side --ignore-all-space --strip-trailing-cr \
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Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt \
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Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt
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```
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